Abstract: A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a floating gate electrode layer located on the first gate insulating film, a first inter-gate insulating film located on the floating gate electrode layer, a control gate electrode layer located on the first inter-gate insulating layer, and a first low-resistance layer located on the control gate electrode layer. Each resistor has a second gate insulating film located on the semiconductor substrate, a first electrode layer located on the second gate insulating film, a second inter-gate insulating film located on the first electrode layer, a second electrode layer located on the second inter-gate insulating film, a second low-resistance layer located on the second electrode layer, and a contact plug connected to the second low-resistance layer.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, a contact region, and first contact plugs. The memory cells include a control gate and a current path. The memory cells are arranged in the memory cell array in the first direction. The contact region is adjacent to the memory cell array in a second direction orthogonal to the first direction. A terminal portion on one end of the control gate is drawn onto the contact region from within the memory cell array. Each of the first contact plugs is formed on the control gate located in the contact region. The first contact plugs are located so as to alternately sandwich a first axis in the first direction.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: A nonvolatile semiconductor memory according to the present invention includes a memory cell transistor which is disposed in a first region and which has a gate electrode of a stacked structure, and a dummy cell which is disposed in a second region neighboring the first region and which has a gate electrode having the same structure as that of the gate electrode of the memory cell transistor. The memory cell transistor and dummy cell are connected to the same word line. The memory cell transistor has a diffusion layer serving as the source/drain region thereof, while the dummy cell does not have the diffusion layer serving as the source/drain region thereof.

Abstract: Strip-shaped alignment marks 14 are juxtaposed with each other in a silicon oxide film 12 formed on a silicon wafer 10. Each alignment mark 14 comprises a plurality of grooves 16 formed side by side in the silicon oxide film 12. An amorphous silicon film 18 is buried in the grooves 16. Thus, the alignment marks 14 are formed in a thus-formed line-and-space pattern. Accordingly, waveforms of detected signals having high contrast and little deformation can be obtained, and alignment of wafers with high accuracy can be realized.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: A semiconductor memory device includes memory cells, a memory cell array, a contact region, and first contact plugs. The memory cells include a control gate and a current path. The memory cells are arranged in the memory cell array in the first direction. The contact region is adjacent to the memory cell array in a second direction orthogonal to the first direction. A terminal portion on one end of the control gate is drawn onto the contact region from within the memory cell array. Each of the first contact plugs is formed on the control gate located in the contact region. The first contact plugs are located so as to alternately sandwich a first axis in the first direction.

Abstract: A nonvolatile semiconductor memory according to the present invention includes a memory cell transistor which is disposed in a first region and which has a gate electrode of a stacked structure, and a dummy cell which is disposed in a second region neighboring the first region and which has a gate electrode having the same structure as that of the gate electrode of the memory cell transistor. The memory cell transistor and dummy cell are connected to the same word line. The memory cell transistor has a diffusion layer serving as the source/drain region thereof, while the dummy cell does not have the diffusion layer serving as the source/drain region thereof.

Abstract: A nonvolatile semiconductor memory includes memory cell transistors and resistors. Each memory cell transistor has source/drain diffusion layers provided in a semiconductor substrate, a first gate insulating film located between the source/drain diffusion layers, a floating gate electrode layer located on the first gate insulating film, a first inter-gate insulating film located on the floating gate electrode layer, a control gate electrode layer located on the first inter-gate insulating layer, and a first low-resistance layer located on the control gate electrode layer. Each resistor has a second gate insulating film located on the semiconductor substrate, a first electrode layer located on the second gate insulating film, a second inter-gate insulating film located on the first electrode layer, a second electrode layer located on the second inter-gate insulating film, a second low-resistance layer located on the second electrode layer, and a contact plug connected to the second low-resistance layer.

Abstract: A semiconductor device according to an example of the present invention includes a first semiconductor region of a first conductivity type, a first MIS transistor of a second conductivity type formed in the first semiconductor region, a second semiconductor region of a second conductivity type, and a second MIS transistor of a first conductivity type formed in the second semiconductor region. A first gate insulating layer of the first MIS transistor is thicker than a second gate insulating layer of the second MIS transistor, and a profile of impurities of the first conductivity type in a channel region of the second MIS transistor has peaks.

Abstract: A semiconductor integrated circuit according to the present invention includes a cell array composed of elements, conductive lines with a pattern of a line & space arranged on the cell array, connecting lines formed upper than the conductive lines, and contact holes which connect the conductive lines to the connecting lines. One end side of the conductive lines sequentially departs from an end of the cell array when heading from one of the conductive lines to another one, the contact holes are arranged at one end side of the conductive lines, and size of the contact holes is larger than width of the conductive lines.

Abstract: A semiconductor memory includes a silicon substrate having a cell array region wherein plural rectangular silicon pillars are formed in rows and columns by a trench having a width of 1a and formed in a lattice form, a storage node formed on at least a surface of a lower portion of the silicon pillar, a well region formed in an upper half above the storage node, a diffusion layer formed on an upper surface of the well region, a capacitor dielectric formed on the storage node to surround the lower portion of the silicon pillar, a plate electrode buried in the lower portion of the trench to substantially the same level as the upper end of the storage node, and a first gate electrode formed on the channel portion via a first gate insulator.

Abstract: A semiconductor memory device has a semiconductor substrate, a first semiconductor region of a first conduction type formed on the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type, formed on the first semiconductor region. A trench capacitors having a trench extends through the first semiconductor region and the second semiconductor region, and is formed such that its top does not reach a top surface of the second semiconductor region, and the trench is formed therein with a conductive trench fill. A pair of gate electrodes is formed on the second semiconductor region, overlying the trench capacitor. A pair of insulating layers is formed to cover each of the pair of gate electrodes. A conductive layer is formed between the pair of insulating layers to self-align to each of the pair of insulating layers.

Abstract: There is proposed a vertical cell transfer transistor comprising a channel region constituted by a monocrystalline silicon layer which is formed by way of epitaxial growth, source-drain regions constituted by n-type diffusion regions which are formed over and below the monocrystalline silicon layer, and an embedded type gate electrode constituted by a word line. In this case, the surface of the insulating film is made flush with the top surface of the n-type diffusion region, i.e. substantially flat and hence free from a stepped portion.

Abstract: A semiconductor memory includes a silicon substrate having a cell array region wherein plural rectangular silicon pillars are formed in rows and columns by a trench having a width of la and formed in a lattice form, a storage node formed on at least a surface of a lower portion of the silicon pillar, a well region formed in an upper half above the storage node, a diffusion layer formed on an upper surface of the well region, a capacitor dielectric formed on the storage node to surround the lower portion of the silicon pillar, a plate electrode buried in the lower portion of the trench to substantially the same level as the upper end of the storage node, and a first gate electrode formed on the channel portion via a first gate insulator.

Abstract: Strip-shaped alignment marks 14 are juxtaposed with each other in a silicon oxide film 12 formed on a silicon wafer 10. Each alignment mark 14 comprises a plurality of grooves 16 formed side by side in the silicon oxide film 12. An amorphous silicon film 18 is buried in the grooves 16. Thus, the alignment marks 14 are formed in a thus-formed line-and-space pattern. Accordingly, waveforms of detected signals having high contrast and little deformation can be obtained, and alignment of wafers with high accuracy can be realized.

Abstract: There is proposed a vertical cell transfer transistor comprising a channel region constituted by a monocrystalline silicon layer which is formed by way of epitaxial growth, source-drain regions constituted by n-type diffusion regions which are formed over and below the monocrystalline silicon layer, and an embedded type gate electrode constituted by a word line. In this case, the surface of the insulating film is made flush with the top surface of the n-type diffusion region, i.e. substantially flat and hence free from a stepped portion.