Abstract: A speech recognition unit (114) and a processor unit (116) of a foreign language learning device (100) receive sentence speech information corresponding to a sentence pronounced by a learner (2) to separate the information into word speech information on the basis of words included in the sentence. The processor unit (116) evaluates the degree of matching (likelihood) of each word speech information with a model speech, and a resultant evaluation is indicated on a display unit (120) on the basis of each word.

Abstract: A speech recognition unit (114) and a processor unit (116) of a foreign language learning device (100) receive sentence speech information corresponding to a sentence pronounced by a learner (2) to separate the information into word speech information on the basis of words included in the sentence. The processor unit (116) evaluates the degree of matching (likelihood) of each word speech information with a model speech, and a resultant evaluation is indicated on a display unit (120) on the basis of each word.

Abstract: In a signal pattern recognition apparatus, a plurality of feature transformation sections respectively transform an inputted signal pattern into vectors in a plurality of feature spaces corresponding respectively to predetermined classes using a predetermined transformation parameter corresponding to each of the classes so as to emphasize a feature of each of the classes, and a plurality of discriminant function sections respectively calculates a value of a discriminant function using a predetermined discriminant function representing a similarity measure of each of the classes for the transformed vectors in the plurality of feature spaces.

Abstract: A speech recognition apparatus includes a data input portion to which input data which is a speech pattern is applied, a score calculation portion calculating a score indicating a possibility of recognition of a partial pattern of the speech pattern based on the estimate of a posteriori odds, an optimization design portion designing optimized parameters for calculating the estimate of the a posteriori odds in the score calculation portion and/or optimized parameters of pruning functions controlling calculation amount in the pruning processing portion, a pruning processing portion pruning the score for making operation efficient, an accumulated score calculating portion accumulating pruned scores to calculate an accumulated score, a recognition result decision portion classifying input data for every class based on the accumulated score and deciding a recognition result, and a recognition result output portion providing the recognition result.

Abstract: The present invention provides an accelerator working in place of a CPU on a motherboard to speed up the processing. The accelerator can realize the high-speed processing even when a clock on the accelerator is not an integral multiple of a clock on the CPU. When a clock frequency of a clock signal CLK on the motherboard is equal to 20 MHz and a maximum frequency of a CPU (3) on an accelerator (100) is equal to 33 MHz, for example, the CPU (3) does not work properly by a doubled clock signal. In such a case, a clock multiplication circuit (3a) multiplies the clock signal CLK by 1.5 times to generate a clock signal CLK15. There are three different patterns in the relationship between the timing of access of the CPU 3 and the timing of access of the motherboard. The accelerator of the invention determines the appropriate timing in each case and allows the access of the CPU 3 to be synchronous with the access of the motherboard.