Abstract: In accordance with an embodiment, an integrated circuit includes a first spin transistor and a second spin transistor. The first spin transistor has a first channel length. The first spin transistor includes a first node and a second node apart from the first node The second spin transistor is connected to the first transistor in series and has a second channel length different from the first channel length. The second spin transistor includes a third node and a fourth node apart from the third node The second node and the fourth node are electrically connected to each other.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes: forming a gate electrode on a substrate via a gate dielectric film; forming a first insulating film on the gate electrode, the first insulating film having a first groove in a central region of the first insulating film; and forming a halo region in the substrate below a side surface of the gate electrode, by injecting an impurity into the substrate through the first insulating film.

Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same const

Abstract: A spin transistor according to an embodiment includes: a first magnetic region supplying a first polarized signal polarized in a first magnetization direction in accordance with a first input signal; a second magnetic region supplying a second polarized signal polarized in a second magnetization direction opposite from the first magnetization direction in accordance with a second input signal, the second input signal being different from the first input signal; and a third magnetic region outputting the first polarized signal supplied from the first magnetic region in accordance with a third input signal, and outputting the second polarized signal supplied from the second magnetic region in accordance with a fourth input signal different from the third input signal.

Abstract: In one embodiment, a transistor includes: a substrate; a source electrode formed on the substrate; a drain electrode formed on the substrate; a graphene film formed between the source electrode and the drain electrode, the graphene film having a semiconductor region including a source side end and a conductor region including a drain side end, a width of the source side end of the graphene film in a channel width direction being narrower than a width of the drain side end of the graphene film in the channel width direction; and a gate electrode formed via a gate insulating film on the semiconductor region of the graphene film and the conductor region of the graphene film. The source electrode is connected to the source side end of the graphene film with a Schottky contact, and the drain electrode is connected to the drain side end of the graphene film with an ohmic contact.

Abstract: According to an embodiment of the present invention, a transistor includes a source electrode, a drain electrode, a graphene film formed between the source electrode and the drain electrode and having a first region and a second region, and a gate electrode formed on the first region and the second region of the graphene film via a gate insulating film. The graphene film functions as a channel. A Schottky junction is formed at a junction between the first region and the second region. The first region has a conductor property, and the second region is adjacent to the drain electrode side of the first region and has a semiconductor property.

Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

Abstract: A semiconductor device according to one embodiment includes: an n-type transistor comprising a first gate electrode formed on a semiconductor substrate via a first gate insulating film, a first channel region formed in the semiconductor substrate under the first gate insulating film, and first source/drain regions formed in the semiconductor substrate on both sides of the first channel region, the first gate electrode comprising a first metal layer and a first conductive layer thereon; and a p-type transistor comprising a second gate electrode formed on the semiconductor substrate via a second gate insulating film, a second channel region formed in the semiconductor substrate under the second gate insulating film, and second source/drain regions formed in the semiconductor substrate on both sides of the second channel region, the second gate electrode comprising a second metal layer and a second conductive layer thereon, the second metal layer being thicker than the first metal layer and having the same const

Abstract: A semiconductor device includes a semiconductor substrate, a p-channel MIS transistor formed on the substrate, the p-channel transistor having a first gate dielectric formed on the substrate and a first gate electrode layer formed on the first dielectric, and an n-channel MIS transistor formed on the substrate, the n-channel transistor having a second gate dielectric formed on the substrate and a second gate electrode layer formed on the second dielectric. A bottom layer of the first gate electrode layer in contact with the first gate dielectric and a bottom layer of the second gate electrode layer in contact with the second gate dielectric have the same orientation and the same composition including Ta and C, and a mole ratio of Ta to a total of C and Ta, (Ta/(Ta+C)), is larger than 0.5.

Abstract: A first element includes a first diffused layer which is formed in the element forming film so as to reach an insulating film, a second diffused layer which is formed in the element forming film so as not to reach the insulating film, and a first body region formed between the first and the second diffused layers. A second element, which is formed on the element forming film so as to be adjacent to the first element, includes the second diffused layer, a third diffused layer which is formed in the element forming film so as to reach the insulating film, and a second body region formed between the second and the third diffused layers. A connection part connects the body region of the first element and the body region of the second element to each other electrically.

Abstract: In one aspect of the present invention, a semiconductor device may include a semiconductor substrate, a gate dielectric layer provided on the semiconductor substrate, a source region provided in the semiconductor substrate, a drain region provided in the semiconductor substrate, and a gate electrode provided on the gate dielectric layer having a metal containing layer and a polycrystalline silicon layer having an impurity ion, the polycrystalline silicon layer provided on the metal containing layer so as to cover an upper surface and side surface of the metal containing layer.

Abstract: According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using sa

Abstract: According to one aspect of the present invention, a semiconductor memory device has: a semiconductor layer formed on an insulating film; and a memory cell array including a matrix arrangement of a plurality of memory cells each made up of first and second transistors connected in series, one side of each memory cell being connected to a bit line and the other side of each memory cell being supplied with a reference potential, and according to another aspect of the present invention, a semiconductor memory device manufacturing method includes: forming an oxide layer and a silicon active layer on a semiconductor substrate; forming an element isolation region for separating said silicon active layer into discrete element-forming regions to be substantially flush with said silicon active layer; forming gate electrode of paired two transistors by depositing a gate electrode material on said silicon active layer and patterning it; injecting predetermined ions into a region for forming a diffusion layer in, using sa

Abstract: A semiconductor device includes a semiconductor layer provided on a semiconductor substrate with an insulating film interposed therebetween. A gate electrode is provided on the semiconductor layer with a gate insulating film interposed therebetween, and a pair of source/drain regions are formed in the semiconductor layer so as to hold a body region under the gate electrode therebetween. A control section supplies voltages to the source/drain regions. The control section supplies the body region in an OFF state and ON state with a first voltage and a second voltage different from the first voltage, respectively. The second voltage is set such that a potential of the body region in the OFF state is substantially the same as a potential of the body region in the ON state.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: A multi-input logic circuit (e.g. a 2-input NAND circuit) mounted on a semiconductor integrated circuit comprises a plurality of voltage-activated transistors which have the same channel conduction type and are electrically connected in series between a power supply terminal and an output terminal. A source region and a body region of at least the voltage-activated transistor connected to the output terminal are electrically connected and have substantially the same potential. The semiconductor integrated circuit has either an SOI or SOS structure.

Abstract: A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.

Abstract: A semiconductor device includes an insulating film provided on a semiconductor substrate and a semiconductor layer provided on the insulating film. An element separating insulating film separates element area. A first gate insulating film is provided on the semiconductor layer in the element area. A gate electrode is provided on the first gate insulating film. Source/drain diffusion layers are formed in the semiconductor layer sandwiching a channel area under the gate electrode therebetween. A potential applying section inducing a leak current which controls the potential of the semiconductor layer comprises a second gate insulating film provided on the semiconductor layer in the element area and a conductive film provided on the second gate insulating film and connected to the gate electrode. The potential applying section is configured so that a leak current through the second gate insulating film is larger than a leak current through the first gate insulating film.

Abstract: A semiconductor device comprises a semiconductor substrate having a first insulator, and a semiconductor channel region formed on the first insulator, wherein the semiconductor channel region comprising at least two first regions both having the first conductivity type, a second region of the conductivity type opposite to the first conductivity type, the second region being provided between the two first regions, a second insulator formed on the second region, a gate electrode formed on the second insulator, a third region having the same conductivity type as that of the second region, the third region being electrically conductive to the second region, a third insulator formed on the third region, the third insulator having a width narrower than the widths of an isolation region for isolating the semiconductor formation region, and a fourth region of the same conductivity type as that of the third region, the fourth region being electrically conductive to the third region.