Abstract: A MOSFET having a drain region consisting of a low concentration impurity diffused layer and a high concentration impurity diffused layer with shallow junction is employed. The variations of the device characteristics are averaged out and the life of the device as a whole is prolonged by increasing the length of the low concentration impurity diffused layer of an N-channel MOSFET, of a circuit whose operating conditions are susceptible to the hot electron effect as in the case of a CMOS address inverter which receives an address signal supplied as a TTL output, and by lowering the drain voltage by an advantageous use of the potential drop due to the resistance of the low concentration impurity diffused layer. The length of the low concentration impurity diffused layer of other MOSFETs is designed by considering the withstand voltage against punch-through between the drain and the source. In this way, it becomes possible to reduce the channel length compared with the case of a device with LDD structure.

Abstract: A semiconductor device having a high density structure and resistant against external abnormal electric charges is disclosd. The semiconductor device comprises an input diffusion resistor coupled to an external terminal and formed in a semiconductor substrate, a diffusion region formed in the semiconductor substrate and a voltage wiring having a contact portion connected to the diffusion region through at least one contact hole formed in an insulating layer covering the diffusion region. A first distance between a first end of the diffusion region close to the diffusion resistor and a first part of the contact portion nearest to the first end is made larger than a distance between a second end opposite to the first end of the diffusion region and a second part of the contact portion nearest to the second end.

Abstract: A semiconductor memory includes a number of static memory cells formed in a substrate. Each memory cell comprises a flip-flop circuit including a pair of first and second insulated gate field effect transistors formed in the substrate. Each of the transistors has a gate connected to one end of the source-drain path of the other transistor of the transistor pair. A pair of first and second load resistors are connected to the above one ends of the first and second transistors, respectively. Each of the load resistors is constituted of a polycrystalline semiconductor layer formed with the intermediary of an insulative layer on the gate of the transistor whose source-drain path is connected is series to the other load resistor. A pair of transfer gate transistors are formed in the substrate and respectively connected to the above one ends of the first and second transistors for selective drive of the flip-flop circuit.

Abstract: A logic circuit on a semiconductor chip having a decoding or a selecting function has at least two input transistors coupled in parallel between an output node and a reference point. Input signals are applied to the input transistors, and an output is derived from the output node. Instead of employing inverters to produce complement signals, a conductivity of one input transistor is made different from that of the other input transistors. The proposed logic circuit can decode or select a combination pattern of input signals without using a complement signal producing circuit. Therefore, the number of circuit elements and signal lines are decreased.

Abstract: An insulated gate type field effect transistor forming one cell of a high density integrated circuit semiconductor memory device and a method for producing the same are disclosed. A channel stopper region of the same conductivity type as the substrate but having a higher impurity concentration is disposed contiguous to the width edge of the channel region, and a thick field oxide film is provided outside of the channel stopper region. The channel stopper region is self-aligned with the width edges of the gate electrode, and an insulator film having a thinner film thickness than that of the thick field oxide film is formed on the channel stopper region. In one embodiment, a second channel stopper region similar to the first is provided at the surface of the substrate under the field oxide film. A capacitor region is associated with the field effect transistor, and together they form a memory cell which is substantially surrounded by an isolating region including the thick field oxide film.

Abstract: An insulated gate type field effect transistor forming one cell of a high density integrated circuit semiconductor memory device and a method for producing the same are disclosed. A channel stopper region of the same conductivity type as the substrate but having a higher impurity concentration is disposed contiguous to the width edge of the channel region, and a thick field oxide film is provided outside of the channel stopper region. The channel stopper region is self-aligned with the width edges of the gate electrode, and an insulator film having a thinner film thickness than that of the thick field oxide film is formed on the channel stopper region. In one embodiment, a second channel stopper region similar to the first is provided at the surface of the substrate under the field oxide film. A capacitor region is associated with the field effect transistor, and together they form a memory cell which is substantially surrounded by an isolating region including the thick field oxide film.

Abstract: A differential type amplifier circuit for use as a sensing amplifier in a memory circuit having a first stage amplifier and a second stage differential type amplifier. The first stage amplifier includes a pair of amplification circuits, the inputs of which are selectively clamped to a predetermined potential. The first stage amplifier functions to amplify low level differential input signals and these amplified signals are applied to the second stage amplifier, the amplified level of the input signals being sufficient to operate the second stage amplifier irrespective of changes in the threshold voltage of the second stage amplifier. Selectively clamping the inputs of the first stage amplifier to a predetermined potential allows the first stage amplifier to accurately amplify the low level input signals due to the fact that the threshold voltage of the first stage amplifier cannot vary from the predetermined potential.