Abstract: An object of the present invention is to provide a water absorbent resin powder for a heat-generating element composition, which suppresses the generation of the aggregates derived from the water absorbent resin and the adhesion of the water absorbent resin in the production of a heat-generating element composition. A present inventive water absorbent resin powder for a heat-generating element composition includes polyacrylic acid (salt)-based water absorbent resin powder which have a bulk specific gravity (specified by JIS K3362) of 0.630 g/cm3 or less, fluid retention capacity without load (CRC) for a 0.9% by weight aqueous solution of sodium chloride (specified by ERT441.01-2) of 32.0 g/g or less, a weight-average particle diameter (specified by sieve classification) of 250 ?m or more, and an amount of a residual glycidyl-based crosslinking agent of 10 ppm or less.

Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Abstract: A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.

Abstract: In a semiconductor memory device, a first load circuit is coupled with the column lines, first dummy cells are connected to a dummy column line, a second load circuit is connected to the dummy column line, a second dummy cell is connected to the dummy column line, and a sense amplifier senses the data stored in the memory cell in accordance with a potential difference between the column line and the dummy column line. In semiconductor memory devices thus arranged, the second dummy cell is set in an on state normally. The connection of the second dummy cell with the dummy line changes a current flowing to the dummy line at the time of row line switching, thereby to hold back a rise of the reference potential at the time of the row line switching.

Abstract: An output buffer produces an output data at an output terminal. A first MOS transistor charges the output terminal toward a first supply potential when turned on. The source and drain of the first MOS transistor are connected between the output terminal and a first supply potential terminal. A second MOS transistor discharges the output terminal toward a second supply potential when turned on. The source and drain of the second MOS transistor are connected between the output terminal and a second supply potential terminal. A resistive element charges the gate of the second MOS transistor toward the first supply potential when turned on. The resistive element is connected between the first supply potential terminal and the gate of the second MOS transistor. The resistance value of the resistive element has nearly a constant value.

Abstract: A nonvolatile semiconductor memory device includes a pulse signal generator for applying a pulse signal to a capacitor, a first diode connected at an anode to the capacitor, a charging circuit for charging the capacitor in a programming mode, a voltage limiter for preventing a potential at the output node from increasing above a predetermined level, memory cells of nonvolatile MOS transistors, a load MOS transistor connected to a high-voltage terminal, a row decoder for selecting a set of memory cells arranged in one row, column gate MOS transistors connected between respective sets of memory cells arranged in one column and the load MOS transistor, a data generator responsive to the voltage at the output node to turn on or off the load MOS transistor, and a column decoder responsive to the voltage at the output node to selectively energize the column gate MOS transistors.

Abstract: A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor.