Patents by Inventor Shigeru Kusunoki
Shigeru Kusunoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11245393Abstract: A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.Type: GrantFiled: December 12, 2016Date of Patent: February 8, 2022Assignee: Mitsubishi Electric CorporationInventors: Sho Tanaka, Shigeru Kusunoki
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Publication number: 20200083879Abstract: A semiconductor device includes a plurality of first transistor cells and a plurality of second transistor cells that are electrically connected in parallel between a collector electrode and an emitter electrode. A gate voltage on each of the plurality of first transistor cells is controlled by a first gate interconnection. A gate voltage on each of the plurality of second transistor cells is controlled by a second gate interconnection. A drive circuit is configured to: apply an ON-voltage of the semiconductor device to each of the first and second gate interconnections when the semiconductor device is turned on; and after a lapse of a predetermined time period since start of application of the ON-voltage, apply an OFF-voltage of the semiconductor device to the second gate interconnection and apply an ON-voltage to the first gate interconnection.Type: ApplicationFiled: December 12, 2016Publication date: March 12, 2020Applicant: Mitsubishi Electric CorporationInventors: Sho TANAKA, Shigeru KUSUNOKI
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Patent number: 9484444Abstract: A semiconductor device has a semiconductor substrate, an insulating film, a semiconductor element and a resistance element. The semiconductor substrate has a first trench. The insulating film covers an inner surface of the first trench. The semiconductor element has an electrode. The resistance element is electrically connected to the electrode to form a resistance to a current flowing through the electrode, and is arranged in the first trench with the insulating film therebetween. Thereby, the semiconductor device can have a resistance element that has a small footprint and can pass a large current with high reliability.Type: GrantFiled: April 28, 2008Date of Patent: November 1, 2016Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Koichi Mochizuki, Minoru Kawakami
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Patent number: 9276094Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: GrantFiled: August 28, 2014Date of Patent: March 1, 2016Assignee: Mitsubishi Electric CorporationInventor: Shigeru Kusunoki
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Patent number: 9041097Abstract: A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer.Type: GrantFiled: March 22, 2013Date of Patent: May 26, 2015Assignee: Mitsubishi Electric CorporationInventor: Shigeru Kusunoki
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Publication number: 20150054024Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: ApplicationFiled: August 28, 2014Publication date: February 26, 2015Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shigeru KUSUNOKI
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Patent number: 8853737Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: GrantFiled: June 11, 2012Date of Patent: October 7, 2014Assignee: Mitsubishi Electric CompanyInventor: Shigeru Kusunoki
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Patent number: 8847290Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.Type: GrantFiled: December 28, 2012Date of Patent: September 30, 2014Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Shinichi Ishizawa
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Publication number: 20140077291Abstract: A semiconductor device includes a channel layer formed on a substrate, an insulating layer formed in contact with the channel layer, an impurity-doped first semiconductor layer formed on an opposite side of the insulating layer from the channel layer, an impurity-doped second semiconductor layer formed on an opposite side of the first semiconductor layer from the insulating layer, and a gate electrode formed on an opposite side of the second semiconductor layer from the first semiconductor layer. A quotient of an impurity density of the first semiconductor layer divided by a relative permittivity of the first semiconductor layer is greater than a quotient of an impurity density of the second semiconductor layer divided by a relative permittivity of the second semiconductor layer.Type: ApplicationFiled: March 22, 2013Publication date: March 20, 2014Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shigeru KUSUNOKI
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Publication number: 20130105866Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.Type: ApplicationFiled: December 28, 2012Publication date: May 2, 2013Inventors: Shigeru KUSUNOKI, Shinichi Ishizawa
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Patent number: 8390069Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: GrantFiled: May 6, 2009Date of Patent: March 5, 2013Assignee: Mitsubishi Electric CorporationInventor: Shigeru Kusunoki
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Patent number: 8373207Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.Type: GrantFiled: October 11, 2010Date of Patent: February 12, 2013Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Shinichi Ishizawa
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Publication number: 20120248499Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: ApplicationFiled: June 11, 2012Publication date: October 4, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shigeru KUSUNOKI
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Patent number: 8253163Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.Type: GrantFiled: October 7, 2010Date of Patent: August 28, 2012Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
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Patent number: 8222699Abstract: A semiconductor device includes a semiconductor substrate including a semiconductor layer, a power device formed in the semiconductor substrate, a plurality of concentric guard rings formed in the semiconductor substrate and surrounding the power device, and voltage applying means for applying successively higher voltages respectively to the plurality of concentric guard rings, with the outermost concentric guard ring having the highest voltage applied thereto.Type: GrantFiled: May 6, 2009Date of Patent: July 17, 2012Assignee: Mitsubishi Electric CorporationInventor: Shigeru Kusunoki
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Patent number: 8164111Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.Type: GrantFiled: October 7, 2010Date of Patent: April 24, 2012Assignee: Mitsubishi Electric CorporationInventors: Shigeru Kusunoki, Junji Yahiro, Yoshihiko Hirota
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Publication number: 20110140179Abstract: A semiconductor device includes: a rectifying element; an electrode pad electrically connected to the rectifying element; and a resistance and a depletion transistor arranged between the rectifying element and the electrode pad, and electrically connected to each other. The semiconductor device has a configuration in which the rectifying element, the resistance, the depletion transistor, and the electrode pad are serially connected. The semiconductor device is configured to generate a gate potential of the depletion transistor based on a difference in potential across the resistance and to produce a depletion layer in a channel of the depletion transistor based on the gate potential. As a result, a semiconductor device having reasonably large current at low voltage and small current at high voltage can be obtained.Type: ApplicationFiled: October 11, 2010Publication date: June 16, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shigeru Kusunoki, Shinichi Ishizawa
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Publication number: 20110140165Abstract: A high voltage semiconductor device includes a semiconductor substrate, a p type base region in a first main surface, an n+ type emitter region in the p type base region, an n+ type cathode region adjacent to an end surface of the semiconductor substrate and not penetrating the semiconductor substrate, a p+ type collector region in a second main surface, a first main electrode, a second main electrode, a third main electrode, and a connection portion connecting the second main electrode and the third main electrode. A resistance between the p type base region and the n+ type cathode region is greater than a resistance between the p type base region and the p+ type collector region. In the high voltage semiconductor device in which an IGBT and a free wheel diode are formed in a single semiconductor substrate, occurrence of a snap-back phenomenon is suppressed.Type: ApplicationFiled: October 7, 2010Publication date: June 16, 2011Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shigeru KUSUNOKI, Junji Yahiro, Yoshihiko Hirota
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Patent number: 7800183Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.Type: GrantFiled: May 12, 2009Date of Patent: September 21, 2010Assignee: Mitsubishi Electric CorporationInventors: Takahiro Okuno, Shigeru Kusunoki
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Publication number: 20100193836Abstract: A semiconductor device includes a substrate of a first conductivity type, a base region of a second conductivity type, a source region of the first conductivity type, a collector region of the second conductivity type, a trench gate, which is formed in a trench via a gate insulation film, an electrically conductive layer, which is formed within a contact trench that is formed through the source region, a source electrode, which is in contact with the electrically conductive layer and the source region, and a latch-up suppression region of the second conductivity type, which is formed within the base region, in contact with the electrically conductive layer, and higher in impurity concentration than the base region. The distance between the gate insulation film and the latch-up suppression region is not less than the maximum width of a depletion layer that is formed in the base layer by the trench gate.Type: ApplicationFiled: May 12, 2009Publication date: August 5, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takahiro Okuno, Shigeru Kusunoki