Patents by Inventor Shigeru Mukasa

Shigeru Mukasa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4631725
    Abstract: An error correcting and detecting system using a parity check H-matrix divided into a plurality of block vectors each including four or three column vectors each having eight elements. In the H-matrix, (i) there are no all "0" vectors; (ii) all column vectors are different from each other; (iii) 8 column vectors each having only one "1" is included therein, (iv) each column vector has an odd number of "1's"; (v) the modulo-2 sum of any three column vectors within any block never equals any column vectors of the H-matrix; (vi) the modulo-2 sum of four column vectors within any block never equals an all "0" vector; and (vii) the modulo-2 sum of eight column vectors within any two blocks never equals an all "0" vector.
    Type: Grant
    Filed: December 27, 1984
    Date of Patent: December 23, 1986
    Assignee: Fujitsu Limited
    Inventors: Moriyuki Takamura, Shigeru Mukasa, Takashi Ibi