Patents by Inventor Shigeru Nakahara
Shigeru Nakahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180260687Abstract: Efficient learning of a neural network can be performed. A plurality of DNNs are hierarchically configured, and data of a hidden layer of a DNN of a first hierarchy machine learning/recognizing device is used as input data of a DNN of a second hierarchy machine learning/recognizing device.Type: ApplicationFiled: April 26, 2016Publication date: September 13, 2018Inventors: Yusuke KANNO, Takeshi SAKATA, Shigeru NAKAHARA
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Patent number: 8086889Abstract: A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.Type: GrantFiled: October 23, 2008Date of Patent: December 27, 2011Assignee: Hitachi, Ltd.Inventors: Yuichi Ito, Yasuhiro Fujimura, Koki Tsutsumida, Shigeru Nakahara
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Patent number: 7719310Abstract: A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance.Type: GrantFiled: January 8, 2009Date of Patent: May 18, 2010Assignee: Hitachi, Ltd.Inventors: Akinori Yokoi, Shigeru Nakahara
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Patent number: 7629827Abstract: The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.Type: GrantFiled: July 2, 2008Date of Patent: December 8, 2009Assignee: Hitachi, Ltd.Inventors: Tetsuya Fukuoka, Shigeru Nakahara, Minoru Motoyoshi
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Patent number: 7612599Abstract: Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.Type: GrantFiled: July 2, 2008Date of Patent: November 3, 2009Assignee: Hitachi, Ltd.Inventors: Minoru Motoyoshi, Yasuhiro Fujimura, Shigeru Nakahara
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Publication number: 20090243658Abstract: A circuit for attaining reduction in AC noise on power supply line caused by IR drop upon use of a decoupling capacitor represented by a cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown, required in the case of a process of a high technology. There is also provided a circuit for suppressing the AC noise on power supply line due to resonance. MOS transistors composing the cross-coupled decoupling capacitor with enhanced resistance to electrostatic breakdown are caused to have lower threshold voltages Vth, thereby reducing a resistance between a source and a drain of each of the MOS transistors, resulting in reduction in IR drop. Further, a damping resistance is effective for suppressing the AC noise on power supply line, and the source-to-drain resistance of each of the MOS transistors is utilized as the damping resistance.Type: ApplicationFiled: January 8, 2009Publication date: October 1, 2009Inventors: Akinori YOKOI, Shigeru Nakahara
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Publication number: 20090113230Abstract: A scan chain group structure in which a group of scan chains formed for each clock tree system in an LSI is subjected to a reconnection process so that the scan chain group is not present across a plurality of clock distribution regions obtained by dividing the clock-supplied region of the clock tree of one system and that the connection distance thereof in the distribution region becomes short, a test clock input mechanism in which test clocks to be input to the distribution regions are independent sub-clock phases, and an on/off mechanism of the clocks to be input to the distribution regions are realized. Further, the scan-in/out and scan test performed at the same time are limited in one region or between single regions, and tests in all regions and between all regions are carried out by a plurality of times of test steps.Type: ApplicationFiled: October 23, 2008Publication date: April 30, 2009Inventors: Yuichi Ito, Yasuhiro Fujimura, Koki Tsutsumida, Shigeru Nakahara
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Publication number: 20090079488Abstract: Clock skew can be reduced by suppressing fluctuation in wiring leads between the final stage clock buffers and the clock distribution circuit for supplying the clock. In view of attaining such reduction of clock skew, an upstream of the clock distribution circuit is formed in an H tree structure and the final stage is formed in a local fishbone structure. A plurality of main clock lines connected to the final stage buffer include a first main clock line and a second main clock line. The number of cell arrangement allowable rows where a plurality of first flip-flops for receiving the clock from the first main clock line are located is different from the number of cell arrangement allowable rows where a plurality first flip-flops for receiving the clock from the second main clock line are located.Type: ApplicationFiled: July 2, 2008Publication date: March 26, 2009Inventors: Minoru MOTOYOSHI, Yasuhiro Fujimura, Shigeru Nakahara
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Publication number: 20090072877Abstract: The semiconductor integrated circuit includes a first subordinate clock tree 802 and a second subordinate clock tree 803, wherein a clock is delayed by a variable delay circuit 805 and inputted into the second subordinate clock tree 803 so that the phases are matched each other of the output clocks from the end clock drivers with the same position in respective trees, thereby reducing clock skew.Type: ApplicationFiled: July 2, 2008Publication date: March 19, 2009Inventors: Tetsuya FUKUOKA, Shigeru Nakahara, Minoru Motoyoshi
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Patent number: 7040707Abstract: A seat back of automotive seat, which comprises an upper seat back portion and a lower seat back portion. A foam padding of the upper seat back portion is greater in hardness than that of the lower seat back portion. A vent element is provided in each of the two seat back portions. The vent element may include a through-hole or a recessed portion, and/or a netted element provided on the lower seat back portion. The upper seat back portion is fixedly connected with the lower seat back portion in an integral manner by means of a connecting element disposed within both of those two seat back portions.Type: GrantFiled: April 13, 2004Date of Patent: May 9, 2006Assignee: Tachi-S Co., Ltd.Inventor: Shigeru Nakahara
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Patent number: 7012848Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: GrantFiled: August 13, 2004Date of Patent: March 14, 2006Assignee: Renesas Technology CorporationInventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Patent number: 7009246Abstract: To reduce the width of isolation between the first and second p channel MIS•FETs driven by different voltages, a first p channel MIS•FET driven by a first supply voltage and a second p channel MIS•FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.Type: GrantFiled: February 6, 2004Date of Patent: March 7, 2006Assignee: Hitachi, Ltd.Inventors: Takahiro Kawata, Shigeru Nakahara, Keiichi Higeta
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Patent number: 7009862Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: GrantFiled: December 15, 2004Date of Patent: March 7, 2006Assignee: Hitachi, Ltd.Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Publication number: 20050225155Abstract: A seat back of automotive seat, which comprises an upper seat back portion and a lower seat back portion. A foam padding of the upper seat back portion is greater in hardness than that of the lower seat back portion. A vent element is provided in each of the two seat back portions. The vent element may include a through-hole or a recessed portion, and/or a netted element provided on the lower seat back portion. The upper seat back portion is fixedly connected with the lower seat back portion in an integral manner by means of a connecting element disposed within both of those two seat back portions.Type: ApplicationFiled: April 13, 2004Publication date: October 13, 2005Applicant: TACHI-S CO., LTD.Inventor: Shigeru Nakahara
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Patent number: 6920071Abstract: A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.Type: GrantFiled: May 14, 2004Date of Patent: July 19, 2005Assignee: Hitachi, Ltd.Inventors: Takahiro Kawata, Shigeru Nakahara, Keiichi Higeta
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Publication number: 20050146947Abstract: Data lines (D0, D1) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC0) coupled to a first comparison data portion (CD0) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (11), and a third transistor (MC1) coupled to a second comparison data line (CD1) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (12). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.Type: ApplicationFiled: December 15, 2004Publication date: July 7, 2005Inventors: Keiichi Higeta, Satoshi Iwahashi, Yoichiro Aihara, Shigeru Nakahara
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Patent number: 6876573Abstract: A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.Type: GrantFiled: August 13, 2004Date of Patent: April 5, 2005Assignee: Renesas Technology CorporationInventors: Keiichi Higeta, Shigeru Nakahara, Hiroaki Nambu
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Publication number: 20050013159Abstract: The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings.Type: ApplicationFiled: August 13, 2004Publication date: January 20, 2005Inventors: Satoshi Iwahashi, Shigeru Nakahara, Takeshi Suzuki, Keiichi Higeta
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Publication number: 20050013160Abstract: Disclosed herein is a semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.Type: ApplicationFiled: August 13, 2004Publication date: January 20, 2005Inventors: Keiichi Higeta, Shigeru Nakahara, Hiroaki Nambu
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Publication number: 20050007170Abstract: An asynchronous control circuit and a semiconductor integrated circuit achieving asynchronous operation and no limitation on the number of ports are offered. In an asynchronous control circuit, by being activated corresponding to at least one access request by acknowledging a plurality of access request signals generated asynchronously to each other and a plurality of input signals corresponding to each of the above-mentioned plurality of access requests, selecting one access request from one or more access requests in the activation mode, acknowledging an input signal corresponding thereto, transmitting the input signal to a memory, acknowledging the input signal corresponding to a non-executed access request after the end the operation corresponding to the input signal, and accessing the aforementioned memory circuit.Type: ApplicationFiled: July 7, 2004Publication date: January 13, 2005Inventors: Shigeru Nakahara, Keiichi Higeta, Takahiro Kawata