Patents by Inventor Shigeru Nose

Shigeru Nose has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11927599
    Abstract: Included are: a main body including an installation part in which a cartridge housing a liquid for treating a test substance contained in a specimen is installed and a detector configured to detect the test substance treated with the liquid within the cartridge installed in the installation part; a lid part arranged rotatably on the main body about a shaft so as to open and close the installation part; a biasing part biasing the lid part in an opening direction; and a plurality of regulators each generating resistance against a biasing force in the opening direction at different timing during an opening motion of the lid part.
    Type: Grant
    Filed: January 25, 2021
    Date of Patent: March 12, 2024
    Assignees: JVCKENWOOD Corporation, SYSMEX CORPORATION
    Inventors: Masahiro Yamamoto, Shigeru Yokota, Hideki Samata, Tomoyuki Nose, Sayuri Tomoda
  • Patent number: 6202180
    Abstract: A memory for controlling a display and which relieves a memory cell by exchanging an address when the memory has defective portions, including an external address input; a first memory circuit which stores an address corresponding to a specified portion of a display; a second memory circuit which stores an address provided to be faulty as a result of a test; and address converting circuit coupled to the external address input and the first and second memory circuits. The converting circuit outputs the address stored in the second memory circuit when an address supplied from the external address input coincides with the address stored in the first memory circuit and outputs the address stored in the first memory circuit when the address supplied from the external address input coincides with the address stored in the second memory circuit.
    Type: Grant
    Filed: June 15, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeru Nose
  • Patent number: 4466097
    Abstract: A control signal-multiplexing circuit for producing various forms of multiplexed control signals from control signals of a plurality of channels. The circuit comprisesa multiplexer for selecting control signals of a plurality of channels by scanning and multiplexing the control signals by time division; anda control signal converting circuit which is supplied with output signals from the multiplexer, converts the signals of the respective channels included in the output signals into various forms of control signals, multiplexes the control signals, and sends forth the multiplexed control signals to the corresponding control lines.
    Type: Grant
    Filed: August 4, 1981
    Date of Patent: August 14, 1984
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Shigeru Nose