Patents by Inventor Shigeru Odanaka

Shigeru Odanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9423361
    Abstract: An inner image generating apparatus includes a first receiver configured to receive an inlet track information and a first passage time of a muon, a second receiver configured to receive an outlet track information and a second passage time of the muon, a displacement calculator configured to calculate a track displacement of a track of the muon based on the inlet and outlet track information, a mean energy calculator configured to calculate a mean energy of the muon based on a time-difference between the first passage and the second passage time, a data integration circuit configured to integrate multiplied data multiplying the track displacement and the mean energy on a projected plane, and an image generating circuit configured to generate an inner image of the structure by identifying a position of matter at the projected plane based on an integrated multiplied data.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: August 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa Sugita, Haruo Miyadera, Kenichi Yoshioka, Naoto Kume, Kohichi Nakayama, Yuichiro Ban, Yoshiji Karino, Kyouichi Fujita, Shigeru Odanaka
  • Publication number: 20150198542
    Abstract: An inner image generating apparatus includes a first receiver configured to receive an inlet track information and a first passage time of a muon, a second receiver configured to receive an outlet track information and a second passage time of the muon, a displacement calculator configured to calculate a track displacement of a track of the muon based on the inlet and outlet track information, a mean energy calculator configured to calculate a mean energy of the muon based on a time-difference between the first passage and the second passage time, a data integration circuit configured to integrate multiplied data multiplying the track displacement and the mean energy on a projected plane, and an image generating circuit configured to generate an inner image of the structure by identifying a position of matter at the projected plane based on an integrated multiplied data.
    Type: Application
    Filed: January 14, 2015
    Publication date: July 16, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tsukasa SUGITA, Haruo MIYADERA, Kenichi YOSHIOKA, Naoto KUME, Kohichi NAKAYAMA, Yuichiro BAN, Yoshiji KARINO, Kyouichi FUJITA, Shigeru ODANAKA
  • Patent number: 7774187
    Abstract: A safety protection instrumentation system for a nuclear reactor is constructed by using digital logic. The digital logic includes functional units in which output logic patterns corresponding to all input logic patterns are verified in advance and a functional module formed by combining the functional units.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: August 10, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mikio Izumi, Toshifumi Hayashi, Teruji Tarumi, Shigeru Odanaka, Naotaka Oda, Toshiaki Ito, Toshifumi Sato, Hideyuki Kitazono, Tatsuyuki Maekawa
  • Publication number: 20090164955
    Abstract: A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.
    Type: Application
    Filed: February 17, 2009
    Publication date: June 25, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikio Izumi, Toshifumi Hayashi, Shigeru Odanaka, Hirotaka Sakai, Naotaka Oda, Toshifumi Sato, Toshiaki Ito
  • Patent number: 7512917
    Abstract: A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: March 31, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mikio Izumi, Toshifumi Hayashi, Shigeru Odanaka, Hirotaka Sakai, Naotaka Oda, Toshifumi Sato, Toshiaki Ito
  • Publication number: 20090055784
    Abstract: A verification method is provided for verifying a safety apparatus including a programmable logic device having a plurality of functional elements. The verification method includes the steps of exhaustively verifying the plurality of functional elements on actual hardware, generating a functional element that is the same as one of the functional elements verified on the actual apparatus using a predetermined hardware description language, independently logic-synthesizing each generated functional element into a plurality of first net lists, generating a connection function between the functional elements using the predetermined hardware description language, logic-synthesizing the generated connection function into a second net list corresponding to the connection function, synthesizing the first net lists with the second net list to generate a third net list, writing a logic circuit into the programmable logic device on the basis of the third net list, and verifying the actual programmable logic device.
    Type: Application
    Filed: February 24, 2006
    Publication date: February 26, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mikio Izumi, Toshifumi Hayashi, Shigeru Odanaka, Hirotaka Sakai, Naotaka Oda, Toshifumi Sato, Toshiaki Ito
  • Publication number: 20070185700
    Abstract: A safety protection instrumentation system for a nuclear reactor is constructed by using a digital logic, in which the digital logic includes functional units in which output logic patterns corresponding to all input logic patterns are verified in advance and a functional module formed by combining the functional units.
    Type: Application
    Filed: March 4, 2005
    Publication date: August 9, 2007
    Applicant: KABUSHIKI KAISHA TOBHIBA
    Inventors: Mikio Izumi, Toshifumi Hayashi, Teruji Tarumi, Shigeru Odanaka, Naotaka Oda, Toshiaki Ito, Toshifumi Sato, Hideyuki Kitazono, Tatsuyuki Maekawa