Abstract: A semiconductor test system has a glitch detection function for detecting glitches in an output signal from a device under test to accurately evaluate the device under test (DUT) . The semiconductor test system includes an event memory for storing event data, an event generator for producing test patterns, strobe signals and expected patterns based on the event data from the event memory, a pin electronics for transmitting the test pattern from the event generator to the DUT and receiving an output signal of the DUT and sampling the output signal by timings of the strobe signals, a pattern comparator for comparing sampled output data with the expected patterns, and a glitch detection unit for receiving the output signal from the DUT and detecting a glitch in the output signal by counting a number of edges in the output signal and comparing an expected number of edges.

Abstract: A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules in a main frame and a measurement module unique to the device under test in a test fixture, thereby achieving a low cost and application specific test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test system main frame to accommodate a combination of two or more tester modules, a test fixture provided on the main frame for electrically connecting the tester modules and a device under test, a measurement module provided in the test fixture for converting signals between the device under test and the tester module depending on the function of the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

Abstract: A semiconductor test system for testing semiconductor devices has a plurality of different tester modules and an algorithmic pattern generator (ALPG) for generating an algorithmic pattern specific to an intended memory in the device under test, thereby achieving a low cost and application specific memory test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, an ALPG module for generating an algorithmic pattern which is specific to the memory; a test system main frame to accommodate a combination of tester module and ALPG module, a test fixture for electrically connecting the tester modules and a device under test, a performance board provided on the test fixture for mounting the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

Abstract: A test system for testing a semiconductor device by having a number of test channels (tester pins) corresponding to the number of terminal pins of the semiconductor device to be tested includes: a tester controller for controlling various operations in the tests system including test patterns to be applied to the device under test, timings and waveforms of the test patterns; a test unit for generating the test patterns and expected value patterns with predetermined timings based on control signals from the tester controller; a pin assignment converter provided between the tester controller and the test unit for providing conversion data showing a conversion relationship between physical pin numbers of the test unit and supplemental tester pin numbers which have been replaced with defective tester pins to the test unit; a test head having drivers for supplying the test patterns from the test unit to the semiconductor device with predetermined amplitudes and comparators for detecting levels of output signals fr

Abstract: A timing signal generation circuit to be used in a semiconductor test system which is not affected by voltage changes or temperature changes.

Abstract: An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the test pattern signals with a timing signal generator set in a condition for generating reference signals. The reference signals and the outputs from the drivers are compared for phase by a phase comparator means. Variable delay means inserted in the paths of the test pattern signal are adjusted by the result of the comparison to suppress skews between the paths of the test pattern signals. Skews in strobe signals, which serve to determine the logic levels of the response signals output from the IC being tested, are also suppressed.

Abstract: A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the address. When a disagreement is detected through the comparison, it is counted; however, the count operation is inhibited if the data read out from the fault-address memory is a fault data. When the counted number exceeds a predetermined value, a fault signal is generated. After the test is terminated, an address counter is operated, the fault-address memory is read out by the content of the address counter, and when fault data is detected from the output read out, the content of the address counter is fetched into the CPU.

Abstract: Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

Abstract: Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.