Abstract: In a disk array configured to distribute and store a plurality of data on a plurality of storage devices, a disk array control device is configured to calculate recovery data for a plurality of storage devices upon detecting an incoherency in a redundant configuration without receiving an abnormality report from a storage device having written predetermined data thereon and to identify the storage device, relating to the correct recovery data determined according to a majority logic, as a storage device inviting an unfinished-writing failure.

Abstract: In a disk array configured to distribute and store a plurality of data on a plurality of storage devices, a disk array control device is configured to calculate recovery data for a plurality of storage devices upon detecting an incoherency in a redundant configuration without receiving an abnormality report from a storage device having written predetermined data thereon and to identify the storage device, relating to the correct recovery data determined according to a majority logic, as a storage device inviting an unfinished-writing failure.

Abstract: A disk array device includes a plurality of disk devices, and a computation portion generating a redundant code data denoting a redundant code able to recover an actual data sent from a higher-level device based on the actual data and operators, when at least part of the actual data is lost. The actual data is written by a predetermined device quantity of first disk devices in a first disk device group composed of disk devices as the first disk devices among the plurality of disk devices. The redundant code data is written by second disk devices of the same quantity as the predetermined device quantity of the first disk devices, in a second disk device group composed of disk devices as the second disk devices other than the first disk devices among the plurality of disk devices.

Abstract: A memory access request is received from a first lower-level device among a plurality of lower-level devices and, when an address of the memory access request is an address in a given range, the memory access request is converted into a setting request from the upper-level device to a second lower-level device among the lower-level devices, the second lower-level device corresponding to the address of the memory access request.

Abstract: A PCI-Express communication system includes a first PCI-Express=PCI-Express bridge connected with an external route complex through a first PCI-Express switch, and configured to perform an address translation on a packet received from the first PCI-Express switch to assign a parameter indicating a first route to a target address of the packet; a second PCI-Express=PCI-Express bridge connected with the external route complex through a second PCI-Express switch, and configured to perform an address translation on a packet received from the second PCI-Express switch to assign a parameter indicating a second route to a target address of the packet; and an address filter configured to limit an address range for the packet received from one of the first PCI-Express=PCI-Express bridge and the second PCI-Express=PCI-Express bridge. A route complex is configured to receive the packet from the address filter.

Abstract: A disk array apparatus includes a plurality of magnetic disks, and a RAID controller that generates redundancy data for host data received from a host apparatus by a primitive polynomial of Galois extension field, generates a redundancy code for the host data and the redundancy data, the redundancy code is a cyclic code calculated by a generating polynomial identical to the primitive polynomial, and writes the host data and the redundancy data to the plurality of magnetic disks.

Abstract: A memory access request is received from a first lower-level device among a plurality of lower-level devices and, when an address of the memory access request is an address in a given range, the memory access request is converted into a setting request from the upper-level device to a second lower-level device among the lower-level devices, the second lower-level device corresponding to the address of the memory access request.

Abstract: A disk array apparatus includes a plurality of magnetic disks, and a RAID controller that generates redundancy data for host data received from a host apparatus by a primitive polynomial of Galois extension field, generates a redundancy code for the host data and the redundancy data, the redundancy code is a cyclic code calculated by a generating polynomial identical to the primitive polynomial, and writes the host data and the redundancy data to the plurality of magnetic disks.

Abstract: A PCI-Express communication system includes a first PCI-Express=PCI-Express bridge connected with an external route complex through a first PCI-Express switch, and configured to perform an address translation on a packet received from the first PCI-Express switch to assign a parameter indicating a first route to a target address of the packet; a second PCI-Express=PCI-Express bridge connected with the external route complex through a second PCI-Express switch, and configured to perform an address translation on a packet received from the second PCI-Express switch to assign a parameter indicating a second route to a target address of the packet; and an address filter configured to limit an address range for the packet received from one of the first PCI-Express=PCI-Express bridge and the second PCI-Express=PCI-Express bridge. A route complex is configured to receive the packet from the address filter.

Abstract: In a switch system including a plurality of switch mechanisms that form a ring topology, each of the switch mechanisms includes an input and output unit that inputs and outputs a packet to and from an outside of a loop; and a gate unit that transmits transmission information including whether there is a packet to be received by one of the switch mechanisms set as a following stage in the loop to the following stage in the loop at predetermined time's intervals. The input and output unit accumulates the packet input from the outside of the loop, and generate transmission information on the accumulated packet. The gate unit transmits the packet accumulated in the input and output unit and the transmission information on the accumulated packet to the following stage in the loop when receiving transmission information, from one of the switch mechanisms set as a preceding stage in the loop, indicating that there is not a packet to receive.

Abstract: Disclosed is a data transmission system in which a set of asymmetrical serial buses are formed by a set of multiplexed unidirectional buses and a reverse-direction sole serial bus. A synchronization signal is superimposed on the signal transmitted over each of the multiplexed unidirectional buses. The multiplexed unidirectional buses are used mainly for data transfer, and the reverse-direction sole serial bus is used for transmitting the control information, such as ACK response, to the data transfer.

Abstract: In a switch system including a plurality of switch mechanisms that form a ring topology, each of the switch mechanisms includes an input and output unit that inputs and outputs a packet to and from an outside of a loop; and a gate unit that transmits transmission information including whether there is a packet to be received by one of the switch mechanisms set as a following stage in the loop to the following stage in the loop at predetermined time's intervals. The input and output unit accumulates the packet input from the outside of the loop, and generate transmission information on the accumulated packet. The gate unit transmits the packet accumulated in the input and output unit and the transmission information on the accumulated packet to the following stage in the loop when receiving transmission information, from one of the switch mechanisms set as a preceding stage in the loop, indicating that there is not a packet to receive.

Abstract: Time series raw data D is regularized by a monitor curve SYt as equivalent to the differential curve of D, made up of trend values calculates in interval expanded consecutingly, trend classification of arbitrary points SYt, are defined to Fn=H(L), ascend(descend) zone, then extracting an object having locus that matches a management purpose, omitting visual chart reading process.

Abstract: In a microprocessor, a type information comparator compares type information of an execution result of an instruction with type information of the type information register corresponding to the data register which is requested by said instruction, and generates an exceptional interrupt in the case of disagreement. An input output execution unit simultaneously receives the data of the data register and the type information of the type information register corresponding to said data register and performs an input and output for an external via an external bus. A calculation execution unit simultaneously receives the data of the data register and the type information of the type information register corresponding to the data register, and executes calculation.

Abstract: There is disclosed a method for selecting a stock name having the highest current value or lowest current value from all the stock names in stock/exchange/merchandise trading and distributing the stock name to investors. Each moving tendency value calculated with a short-term interval p+1 and further interval 2p+1, 4p+1, 8p+1, 16p+1 is standardized, its central portion is divided/set into a division for letting trading go by, a high-value division F, F2, F3, F4, F5=H, and a low-value division F, F2, F3, F4, F5=L, and a fluctuation of a tendency value curve of a stock price locus leading to the current value is synthesized/indicated as F5+F4+F3+F2+F. At the present point of time when an approach signal or an extreme value signal TU, XU is detected and the division shifts to F, F2, F3, F4, F5=H, the stock name is transmitted/distributed as a stock name having the extreme value with a long ascending time.

Abstract: The multi-processor system of the present invention comprises: a plurality of processors; a shared memory shared by the processors; and an exclusive controller for arbitrating the use of the shared memory by the processors. The shared memory has an identifier storage region for storing an identifier indicating the last processor which has updated a block in the shared memory, and the processor which is to process data in the block in the shared memory compares its own identifier with the identifier stored in the identifier storage region, and does not refer to the shared memory but refers an exclusively usable memory of the processor when its own identifier coincides with the identifier in the identifier storage region.

Abstract: A control mechanism of a disk controller measures read and write hit rates for each data item in the cache memory. The intended storage location on a disk of each data item in the cache is compared to the current head position of a recording/reproduction head on the disk and the distance therebetween is calculated. A selector selects for write-back data from among the data items stored in the cache in accordance with the read hit rate, write hit rate and the calculated distance. The selector also selects an item for write back based on a longest predicted data transfer time.