Patents by Inventor Shigeru Sugioka

Shigeru Sugioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220059346
    Abstract: A method including forming an insulating film over first, second, third and fourth regions of a semiconductor substrate; forming a polyimide film on the insulating film; and patterning the polyimide film with a lithography method using a photomask including at least a first region of a first transmittance rate, a second region of a second transmittance rate, a third region. having a shading material, and a fourth region, wherein the first, second, third and fourth regions of the photomask correspond to the first, second, third and fourth regions of the semiconductor substrate, respectively.
    Type: Application
    Filed: August 24, 2020
    Publication date: February 24, 2022
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Wataru Hoshino, Shigeru Sugioka, Toshiyuki Maenosono
  • Publication number: 20220020750
    Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.
    Type: Application
    Filed: September 30, 2021
    Publication date: January 20, 2022
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Patent number: 11211347
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: December 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20210391279
    Abstract: A semiconductor device includes a semiconductor substrate; and a multilevel wiring structure on the semiconductor substrate, the multilevel wiring structure including at least an intermediate metal layer over the semiconductor substrate and an uppermost metal layer over the intermediate metal layer, and the multilevel wiring structure being divided into a main circuit portion and a scribe portion surrounding the main circuit portion; wherein the scribe portion of the multilevel wiring layer includes at least a metal pad exposed in the intermediate metal layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shigeru Sugioka, Keizo Kawakita, Hidenori Yamaguchi, Bang Ning Hsu
  • Publication number: 20210375778
    Abstract: A semiconductor device includes a semiconductor substrate; a first insulating film and a second insulating film provided above the semiconductor substrate; a low-k film provided between the first insulating film and the second insulating film; an element formation region in which elements included in an electric circuit are formed in the semiconductor substrate; a scribe region provided around the element formation region; a cut portion provided on the outer periphery of the scribe region; and a groove formed between the cut portion and the element formation region, wherein the groove penetrates through the low-k film.
    Type: Application
    Filed: May 27, 2020
    Publication date: December 2, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita
  • Publication number: 20210364911
    Abstract: A semiconductor device includes a semiconductor substrate having a semiconductor substrate having a main surface including a first portion; a redistribution layer provided over the first portion of the main surface of the semiconductor substrate; an insulating layer covering the first portion of the main surface of the semiconductor substrate and the redistribution layer; and a first polyimide film covering the insulating layer; wherein the polyimide film has a substantially flat upper surface.
    Type: Application
    Filed: May 19, 2020
    Publication date: November 25, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Hidenori Yamaguchi, Keizo Kawakita, Shigeru Sugioka
  • Publication number: 20210351133
    Abstract: A semiconductor device includes a main circuit region; and a scribe region surrounding the main circuit region; wherein the main circuit region and the scribe region comprises first and second insulating films and a low-k film formed therebetween; and wherein the low-k film of the scribe region includes a plurality of cavities lining along a border between. the main circuit region and the scribe region.
    Type: Application
    Filed: May 11, 2020
    Publication date: November 11, 2021
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shigeru Sugioka, Hidenori Yamaguchi, Noriaki Fujiki, Keizo Kawakita, Raj K. Bansal
  • Patent number: 11158640
    Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: October 26, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Patent number: 10943841
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: March 9, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20210050301
    Abstract: An apparatus comprising a multilevel wiring structure comprising aluminum interconnections. The aluminum interconnections comprise a first portion, a second portion, and a third portion, where the second portion is between the first portion and the third portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. A memory device comprising a memory array comprising memory cells and a control logic component electrically connected to the memory array. At least one of the memory cells comprises a multilevel wiring structure comprising interconnect structures, where the interconnect structures comprise a first portion, a second portion adjacent to the first portion, and a third portion adjacent to the second portion. The third portion comprises a greater width in a lateral direction than a width in the lateral direction of the second portion. Related apparatus, memory devices, and methods are also disclosed.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 18, 2021
    Inventors: Shigeru Sugioka, Noriaki Fujiki, Keizo Kawakita, Takahisa Ishino
  • Publication number: 20210020592
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Application
    Filed: October 1, 2020
    Publication date: January 21, 2021
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10847482
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20200335504
    Abstract: An apparatus comprising first and second interconnections spaced apart from one another, an interlayer insulating material over the first and second interconnections, first and second contacts in the interlayer insulating material and spaced apart from one another, third and fourth interconnections over the interlayer insulating material and spaced apart from one another, and compensation capacitors in a capacitor region. The third interconnections are coupled with the first interconnections through the first contacts and the fourth interconnections are coupled with the second interconnections through the second contacts. The compensation capacitors comprise lower electrodes over the interlayer insulating material, dielectric materials over the lower electrodes, and upper electrodes over the dielectric materials. The lower electrodes comprise edge portions in contact with the second contacts.
    Type: Application
    Filed: April 22, 2019
    Publication date: October 22, 2020
    Inventors: Shigeru Sugioka, Keizo Kawakita
  • Patent number: 10727271
    Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source includes first linear portions and second linear portions extending at an acute angle to each of the first direction and the second direction. Electronic systems include such a memory device operably coupled to a processor, to which at least one input device and at least one output device is operably coupled. Methods of forming such an array of memory cells including a common source.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: July 28, 2020
    Assignee: Micron Trechnology, Inc.
    Inventor: Shigeru Sugioka
  • Publication number: 20200227327
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10651100
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: May 12, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20190355682
    Abstract: In some embodiments, a method of forming an opening in a material comprises forming RIM over target material. Radiation is impinged onto the RIM through a masking tool over a continuous area of the RIM under which a target-material opening will be formed. The masking tool during the impinging allows more radiation there-through onto a mid-portion of the continuous area of the RIM in a vertical cross-section than onto laterally-opposing portions of the continuous area of the RIM that are laterally-outward of the mid-portion of the RIM in the vertical cross-section. After the impinging, the RIM is developed to form a RIM opening that has at least one pair of laterally-opposing ledges laterally-outward of the mid-portion of the RIM in the vertical cross-section elevationally between a top and a bottom of the RIM opening.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Publication number: 20190355631
    Abstract: A substrate comprises a pair of immediately-adjacent integrated-circuit dies having scribe-line area there-between. At least one of the dies comprises insulting material above integrated circuitry. The insulating material has an opening therein that extends elevationally inward to an upper conductive node of integrated circuitry within the one die. The one die comprises a conductive line of an RDL above the insulating material. The RDL-conductive line extends elevationally inward into the opening and is directly electrically coupled to the upper conductive node. The insulating material has a minimum elevational thickness from an uppermost surface of the upper conductive node to an uppermost surface of the insulating material that is immediately-adjacent the insulating-material opening. Insulator material is above a conductive test pad in the scribe-line area. The insulator material has an opening therein that extends elevationally inward to an uppermost surface of the conductive test pad.
    Type: Application
    Filed: May 16, 2018
    Publication date: November 21, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Shigeru Sugioka, Kiyonori Oyu, Hiroshi Toyama, Jung Chul Park, Raj K. Bansal
  • Patent number: 10453895
    Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source electrically couples memory cells of the array in both the first direction and the second direction. Electronic systems include such a memory device electrically coupled to a processor, to which at least one input device and at least one output device is electrically coupled. Methods of forming such an array of memory cells including a common source.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventor: Shigeru Sugioka
  • Publication number: 20180269254
    Abstract: Memory devices include an array of memory cells including magnetic tunnel junction regions. The array of memory cells includes access lines extending in a first direction and data lines extending in a second direction transverse to the first direction. A common source includes first linear portions and second linear portions extending at an acute angle to each of the first direction and the second direction. Electronic systems include such a memory device operably coupled to a processor, to which at least one input device and at least one output device is operably coupled. Methods of forming such an array of memory cells including a common source.
    Type: Application
    Filed: May 17, 2018
    Publication date: September 20, 2018
    Inventor: Shigeru Sugioka