Abstract: It is an object of the present invention to provide a sanitary upper garment with grips capable of smoothly performing holding/putting-down operation and reducing a burden on a wearer by assisting holding a child. The upper garment with grips includes an upper garment body 10 having sleeves, and grips 20 provided on the upper garment body 10, and the grips 20 has a plurality of sleeve grips provided to right and left sleeves 11. By having a plurality of sleeve grips on the sleeves 11 of the upper garment body 10 in this manner, a wearer X can grasp a grip in a preferred position to support a holding child Y and a lifted load and directly distribute a load on the arm to reduce the burden on the wearer X.

Abstract: To achieve an optical RZ signal generator having a simple constitution in which the number of components is significantly reduced in comparison with a conventional one, an optical RZ signal generator according to the present invention comprises a steady-state power laser light source 103 and a Mach-Zehnnder optical modulator 104 for performing intensity modulation on the basis of an electric signal supplied from an electric data signal input terminal 101 with being connected to an output of the steady-state power laser light source 103. The electric signal is a binary voltage signal and insertion loss of the Mach-Zehnnder optical modulator is preset so as to shift from a first state to a second state other than the first one and then returns to the first state in a logic level transition process of the binary voltage signal.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.

Abstract: In a memory drive system of a DC type of plasma display panel, scan signals are applied to scan electrodes connected to the DC type of plasma display panel, with the scan signals each comprising a priming scan pulse for generating the priming discharge, a write scan pulse for generating the write discharge, and a sustain pulse train for generating the sustain discharge. The priming scan pulse, the write scan pulse and the sustain pulse train are sequentially shifted on a time basis for each scan signal. To each of the data electrodes connected to the DC type of plasma display panel, a data signal is applied in which, only when the write discharge is not to be generated, is a non-write pulse formed, which offers a turn-off level during an applying period of time for the write scan pulse, and which maintains a turn-on level when the write discharge is to be generated and during other periods of time except the applying period of time for the write scan pulse.

Abstract: In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.

Abstract: In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

Abstract: In a logic simulator for simulating a logic circuit described by sentences, each specifying at least one operation and at least two variables which should be subjected to the operation, a model memory memorizes operators for carrying out the operations for the sentences. A variable memory memorizes initial values of the variables for the sentences. A sentence calculating unit calculates one of the sentences as a current sentence at a time to produce a result of calculation by using those of the operators and the initial values which are related to the current sentence. A data or result memory memorizes previous data or initial result values calculated before calculation of the current sentence. The result of calculation is substituted for those of the previous data or the initial result values which are related to the current sentences.

Abstract: In a fault simulator for simulating a logic circuit model which is operable in response to first through n-th input pattern signals, a signal generating circuit implemented by hardware generates the first through the n-th input pattern signals. The logic circuit model is assorted into first through m-th levels and is defined by first through p-th faults. The fault simulator carries out a plurality of simulations at the same time in each of the first through the m-th levels. When the simulation proceeds to the m-th level, the fault simulator produces a simulation result signal representative of detected faults and a correct value. The fault simulator simulates the first through the p-th faults by the use of each of the first through the n-th input pattern signals.

Abstract: In a logic simulator for simulating a logic circuit model which is operable in response to first through k-th input logic signals where k is a natural number greater than unity, the first through k-th input logic signals are read out of a memory to simultaneously carry out first through k-th simulations of the logic circuit model and to simultaneously produce first through k-th simulation result signals. The simulation result signals are compared with one another to detect an event different from a normal event and to carry out further simulations in connection with the different event. When the model is assorted into first through last ranks, the simultaneous simulations proceed from the first rank to the last rank one by one. A plurality of faults can also be simultaneously simulated by the logic simulator with a single one of the input logic signals set to the model.

Abstract: In a hardware simulator for use in successively carrying out simulations of gates arranged in a logic circuit, a plurality of connection data signals are stored in a connection memory to specify connections among the gates while a plurality of gate species data signals are stored in a gate species memory to represent each species of the gates. Responsive to a test data signal, a processing circuit executes each simulation of the gates with references to both the connection and the gate species data signals read out of the connection memory and the gate species memory, and supplies a simulation result signal to one of several status memories. Each simulation may be carried out in a pipeline fashion. Alternatively, the connection data signals can be derived from a modified logic circuit obtained by rearranging the logic circuit.

Abstract: This apparatus is used for splicing the ends of the spun yarn by inserting the yarn ends into an air jet nozzle having one or a plurality of air jet pipes, in which they are doubled and subjected to an air jet to join each other. Yarn end cutting and holding devices for the top yarn and the bottom yarn are disposed at the both ends of a yarn inserting hole of the air jet nozzle. An automatic yarn inserting device may be provided with the apparatus to introduce the yarn ends into the yarn inserting hole and into the yarn end cutting and holding devices.

Abstract: Broken ends of a spun yarn are introduced into a hole of an air nozzle device from upper end and lower end of the hole respectively and the yarns are doubled. The doubled yarns are slightly slacked and subjected to air jetting by the air nozzle device to produce a spliced joint. The distribution of twists inherent of spun yarns is changed in the region of the spliced joint by twists imparted to the yarns by the air jet nozzle and at least one fixed portion of the new twist distribution is formed in the spliced joint.