Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.

Abstract: The analog signal input circuit comprises an analog-to-digital circuit and a conversion error measuring circuit. The conversion error measuring circuit comprises the following elements. A first switching device is provided between an analog signal input terminal and the sample/hold circuit for disconnecting the analog-to-digital circuit from the analog signal input terminal when measuring a conversion error value. A reference voltage generation circuit is connected via a second switching device between the first switching device and the sample/hold circuit. The correction reference voltage generation circuit generates a correction reference voltage in relation to the A/D conversion reference voltage. The second switching device is operated to connect the analog-to-digital circuit to the correction reference voltage generation circuit when measuring the conversion error value.

Abstract: An apparatus for fractionally measuring a polymer comprising: a flow path change valve unit A having an inlet for pouring a sample polymer solution, a loop for metering the sample polymer solution, an internal standard solution pouring mechanism including a loop for metering the liquid and a valve for pouring the liquid, and a valve for changing the system flow path; a composition fractionation unit B which is provided with a column filled with a filler, and which permits the polymer dissolved in the sample polymer solution transferred from the loop for metering the sample polymer solution to precipitate on the filler, and then fractionally dissolves the polymer by stepwisely raising the temperature in the column; a molecular size fractionation unit C which is provided with a column filled with a filler, and which fractionates, depending upon the molecular size, the sample polymer fraction solution which has undergone composition fractionation in the unit B and which is batchwisely transferred therefrom; a so

Abstract: An interrupt control circuit is configured as a memory circuit to output interrupt vector information in response to multilevel interrupt requests for a CPU. The interrupt control circuit is provided with a plurality of interrupt vector generators configured as a memory matrix array. Each interrupt vector generator effects self-addressing based on the contents of a memory cell functioning as a latch circuit in which is stored an interrupt request and the contents of a memory cell functioning as a mask register in which interrupt control information is stored. The interrupt control circuit is further provided with a single output buffer commonly coupled to memory cells constituting each interrupt vector generator, thereby providing access to a self-addressed interrupt vector generator to concurrently output the interrupt vector information from the respective memory cells to a data bus via the single output buffer.

Abstract: For preventing a semiconductor substrate from undesirable discharging of electric charges, there is disclosed a semiconductor memory device fabricated on the semiconductor substrate and having a read-out mode and a write-in mode, comprising: (a) a plurality of memory cells arranged in rows and columns and having read only memory cells and random access memory cells; (b) a plurality of word lines each operative to activate the memory cells of each row in the read-out mode and the write-in mode; (c) a plurality of first data lines each operative to propagate a voltage level; (d) a plurality of second data lines each paired with each of the first data lines to form a data line pair coupled to the memory cells of each column, each of the second data lines being operative to propagate the complementary voltage level of the voltage level on the first data line, the voltage level and the complementary voltage level representing a bit of data information; and (d) a plurality of read-write buffer circuits each coupled