Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.

Abstract: There is provided a serial reception circuit that can suppress the occurrence of a bit error due to long-period jitter while suppressing the power consumption. A serial reception circuit for receiving a serial signal in synchronization with a clock signal samples the serial signal in synchronization with multiphase sampling clock signals out of phase with the clock signal, determines based on sampled signals that a sampling phase having little effect of phase variation of the serial signal on a sampling result is an optimum phase, performs a reception operation in which a signal sampled by the optimum phase is reception data, and has, as determination operations for the optimum phase, a first mode and a second mode in which optimality of an optimum phase determined in the first mode is determined based on a sampling result of a reduced number of samplings.