Abstract: An image processing device includes: a first matching circuit to determine whether an image matrix of image data of a first resolution matches a first pattern, and output a first determination result; a first converting circuit to, if the image matrix matches the first pattern, replace a target pixel of the image matrix with a first pixel pattern of a second resolution, and output first image data of the second resolution; a second converting circuit to convert the image data of the first resolution into image data of the second resolution, and output second image data of the second resolution; a detecting circuit to detect whether the target pixel is included in a fine line structure, and output a detection result; and a selecting circuit to output one of the first image data and the second image data based on the first determination result and the detection result.

Abstract: A self-test circuit is driven by a multiphase clock signal which includes N number of clock signals in same cycle having phases from first to N-th phases each phase-shifted by 1/N of the cycle. The self-test circuit includes a data selecting circuit, a serialization circuit, and a logical test circuit. The data selecting circuit switches input data that are input as M-bit wide parallel data to the self-test circuit, between normal data and test data for logical test. The serialization circuit performs serial conversion of the input data in N-parallel manner and outputs bits in N-parallel manner, as a single serial output signal at timing corresponding to each phase. In synchronization with timing corresponding to each phase, the logical test circuit imports the serial output signal as N-parallel bit strings each having length equal to M/N number of bits and performs a bit logical test for M number of bits.

Abstract: An image processing device includes: a first matching circuit to determine whether an image matrix of image data of a first resolution matches a first pattern, and output a first determination result; a first converting circuit to, if the image matrix matches the first pattern, replace a target pixel of the image matrix with a first pixel pattern of a second resolution, and output first image data of the second resolution; a second converting circuit to convert the image data of the first resolution into image data of the second resolution, and output second image data of the second resolution; a detecting circuit to detect whether the target pixel is included in a fine line structure, and output a detection result; and a selecting circuit to output one of the first image data and the second image data based on the first determination result and the detection result.

Abstract: A self-test circuit is driven by a multiphase clock signal which includes N number of clock signals in same cycle having phases from first to N-th phases each phase-shifted by 1/N of the cycle. The self-test circuit includes a data selecting circuit, a serialization circuit, and a logical test circuit. The data selecting circuit switches input data that are input as M-bit wide parallel data to the self-test circuit, between normal data and test data for logical test. The serialization circuit performs serial conversion of the input data in N-parallel manner and outputs bits in N-parallel manner, as a single serial output signal at timing corresponding to each phase. In synchronization with timing corresponding to each phase, the logical test circuit imports the serial output signal as N-parallel bit strings each having length equal to M/N number of bits and performs a bit logical test for M number of bits.