Patents by Inventor Shigeru Umeno
Shigeru Umeno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11121003Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.Type: GrantFiled: June 12, 2018Date of Patent: September 14, 2021Assignee: SUMCO CorporationInventors: Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
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Patent number: 11094557Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?m from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.Type: GrantFiled: June 19, 2018Date of Patent: August 17, 2021Assignee: SUMCO CORPORATIONInventors: Toshiaki Ono, Shigeru Umeno
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Publication number: 20200105542Abstract: Provided is a method of accurately predicting the thermal donor formation behavior in a silicon wafer, a method of evaluating a silicon wafer using the prediction method, and a method of producing a silicon wafer using the evaluation method. The method of predicting the formation behavior of thermal donors, includes: a first step of setting an initial oxygen concentration condition before performing heat treatment on the silicon wafer for reaction rate equations based on both a bond-dissociation model of oxygen clusters associated with the diffusion of interstitial oxygen and a bonding model of oxygen clusters associated with the diffusion of oxygen dimers; a second step of calculating the formation rate of oxygen clusters formed through the heat treatment using the reaction rate equations; and a third step of calculating the formation rate of thermal donors formed through the heat treatment based on the formation rate of the oxygen clusters.Type: ApplicationFiled: June 12, 2018Publication date: April 2, 2020Applicant: SUMCO CorporationInventors: Kazuhisa Torigoe, Shigeru Umeno, Toshiaki Ono
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Publication number: 20200083060Abstract: A silicon wafer having a BMD density of 5×108/cm3 or more and 2.5×1010/cm3 or less in a region of 80 ?m to 285 ?M from the wafer surface when the silicon wafer is heat-treated at a temperature X (° C., 700° C.?X?1000° C.) for a time Y (min) and then subjected to an infrared tomography method in which the laser power is set to 50 mW and the exposure time of a detector is set to 50 msec. The time Y and the temperature X satisfy Y=7.88×1067×X?22.5.Type: ApplicationFiled: June 19, 2018Publication date: March 12, 2020Applicant: SUMCO CORPORATIONInventors: Toshiaki ONO, Shigeru UMENO
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Patent number: 10177008Abstract: This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a PV region are destroyed or reduced, and that has a gettering site.Type: GrantFiled: January 14, 2014Date of Patent: January 8, 2019Assignee: SUMCO CORPORATIONInventors: Takashi Nakayama, Takeo Katoh, Kazumi Tanabe, Shigeru Umeno
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Publication number: 20160322233Abstract: This method for manufacturing a silicon wafer includes: a first heat treatment step of performing RTP treatment on the silicon wafer in an oxidizing atmosphere; a step of removing a region in the silicon wafer in which an oxygen concentration increases in the first heat treatment step; a second heat treatment step of performing, after performing this removing step, RTP treatment on the silicon wafer in a nitriding atmosphere or an Ar atmosphere; and a step of removing, after performing the second heat treatment step, a region in the silicon wafer in which an oxygen concentration decreases in the second heat treatment step. This method enables the manufacture of a silicon wafer in which latent defects such as OSF nuclei and oxygen precipitate nuclei existing in a PV region are destroyed or reduced, and that has a gettering site.Type: ApplicationFiled: January 14, 2014Publication date: November 3, 2016Applicant: SUMCO CORPORATIONInventors: Takashi NAKAYAMA, Takeo KATOH, Kazumi TANABE, Shigeru UMENO
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Patent number: 9412622Abstract: An epitaxial silicon wafer cut from a silicon single crystal grown by the Czochralski method, and having a diameter of 300 mm or more. In this epitaxial silicon wafer, the time required to cool every part of the silicon single crystal during the growth from 800° C. down to 600° C. is set to 450 minutes or less, the interstitial oxygen concentration is from 1.5×1018 to 2.2×1018 atoms/cm3 (old ASTM standard), the entire surface of the cut silicon wafer is composed of a COP region, and the BMD density in the bulk of the epitaxial wafer after a heat treatment at 1000° C. for 16 hours is 1×104/cm2 or less. In this epitaxial silicon wafer, even if the thermal process in a semiconductor device fabrication process is a low temperature thermal process, epitaxial defects do not occur, as well as sufficient gettering capability being obtainable.Type: GrantFiled: October 9, 2013Date of Patent: August 9, 2016Assignee: SUMCO CORPORATIONInventors: Toshiaki Ono, Shigeru Umeno
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Publication number: 20160042974Abstract: An epitaxial silicon wafer cut from a silicon single crystal grown by the Czochralski method, and having a diameter of 300 mm or more. In this epitaxial silicon wafer, the time required to cool every part of the silicon single crystal during the growth from 800° C. down to 600° C. is set to 450 minutes or less, the interstitial oxygen concentration is from 1.5×1018 to 2.2×1018 atoms/cm3 (old ASTM standard), the entire surface of the cut silicon wafer is composed of a COP region, and the BMD density in the bulk of the epitaxial wafer after a heat treatment at 1000° C. for 16 hours is 1×104/cm2 or less. In this epitaxial silicon wafer, even if the thermal process in a semiconductor device fabrication process is a low temperature thermal process, epitaxial defects do not occur, as well as sufficient gettering capability being obtainable.Type: ApplicationFiled: October 9, 2013Publication date: February 11, 2016Applicant: SUMCO CORPORATIONInventors: Toshiaki ONO, Shigeru UMENO
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Patent number: 8771415Abstract: By determining a control direction of a pulling-up velocity without using a position or a width of an OSF region as an index, a subsequent pulling-up velocity profile is fed back and adjusted. A silicon single crystal ingot that does not include a COP and a dislocation cluster is grown by a CZ method, a silicon wafer is sliced from the silicon single crystal ingot, reactive ion etching is performed on the silicon wafer in an as-grown state, and a grown-in defect including silicon oxide is exposed as a protrusion on an etching surface. A growing condition in subsequent growing is fed back and adjusted on the basis of an exposed protrusion generation region. As a result, feedback with respect to a nearest batch can be performed without performing heat treatment to expose a defect.Type: GrantFiled: October 23, 2009Date of Patent: July 8, 2014Assignee: Sumco CorporationInventors: Shigeru Umeno, Keiichiro Hiraki, Hiroaki Taguchi
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Patent number: 8617311Abstract: In this silicon single crystal wafer for IGBT, COP defects and dislocation clusters are eliminated from the entire region in the radial direction of the crystal, the interstitial oxygen concentration is 8.5×1017 atoms/cm3 or less, and variation in resistivity within the wafer surface is 5% or less. This method for manufacturing a silicon single crystal wafer for IGBT includes introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5×1017 atoms/cm3 or less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The pulled silicon single crystal is irradiated with neutrons so as to dope with phosphorous; or an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so that the phosphorous concentration in the silicon single crystal is 2.9×1013 to 2.Type: GrantFiled: February 20, 2007Date of Patent: December 31, 2013Assignee: Sumco CorporationInventors: Toshiaki Ono, Shigeru Umeno, Wataru Sugimura, Masataka Hourai
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Patent number: 8460463Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3 and with a diameter of a COP occurring region not more than a diameter of a crystal, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, and mirror polishing the other main surface of the wafer.Type: GrantFiled: August 20, 2009Date of Patent: June 11, 2013Assignee: Sumco CorporationInventors: Shigeru Umeno, Manabu Nishimoto, Masataka Hourai
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Patent number: 8231852Abstract: It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.Type: GrantFiled: May 14, 2010Date of Patent: July 31, 2012Assignee: Sumco CorporationInventors: Wataru Itou, Takashi Nakayama, Shigeru Umeno, Hiroaki Taguchi, Yasuo Koike
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Patent number: 8105436Abstract: A single crystal silicon wafer for use in the production of insulated gate bipolar transistors is made of single crystal silicon grown by the Czochralski method and has a gate oxide with a film thickness of from 50 to 150 nm. The wafer has an interstitial oxygen concentration of at most 7.0×1017 atoms/cm3, a resistivity variation within the plane of the wafer of at most 5% and, letting tox (cm) be the gate oxide film thickness and S (cm2) be the electrode surface area when determining the TZDB pass ratio, a density d (cm?3) of crystal originated particles (COP) having a size at least twice the gate oxide film thickness which satisfies the formula d??ln(0.9)/(S·tox/2). The wafers have an increased production yield and a small resistivity variation.Type: GrantFiled: September 22, 2008Date of Patent: January 31, 2012Assignee: Sumco CorporationInventor: Shigeru Umeno
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Publication number: 20110052923Abstract: An epitaxial wafer is produced by a method comprising steps of growing a silicon single crystal ingot having a given oxygen concentration through Czochralski method, cutting out a wafer from the silicon single crystal ingot, subjecting the wafer to a heat treatment at a given temperature for a given time, and epitaxially growing the wafer.Type: ApplicationFiled: August 24, 2010Publication date: March 3, 2011Applicant: SUMCO CORPORATIONInventors: Shigeru Umeno, Toshiaki Ono, Wataru Sugimura
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Patent number: 7846252Abstract: A silicon wafer for an IGBT is produced by forming an ingot having an interstitial oxygen concentration [Oi] of not more than 7.0×1017 atoms/cm3 by the Czochralski method; doping phosphorus in the ingot by neutron beam irradiation to the ingot; slicing a wafer from the ingot; performing annealing of the wafer in an oxidizing atmosphere containing at least oxygen at a temperature satisfying a predetermined formula; and forming a polysilicon layer or a strained layer on one side of the wafer.Type: GrantFiled: October 24, 2007Date of Patent: December 7, 2010Assignee: Sumco CorporationInventors: Shigeru Umeno, Yasuhiro Oura, Koji Kato
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Publication number: 20100290971Abstract: It is possible to provide a silicon wafer that as well as being free of COPs and dislocation clusters, has defects (grown-in defects including silicon oxides), which are not overt in an as-grown state, such as OSF nuclei and oxygen precipitate nuclei existing in the PV region, to be vanished or reduced, by adopting a method for producing a silicon wafer, the method comprising the steps of: growing a single crystal silicon ingot by the Czochralski method; cutting a silicon wafer out of the ingot; subjecting the wafer to an RTP at 1,250° C. or more for 10 seconds or more in an oxidizing atmosphere; and removing a grown-in defect region including silicon oxides in the vicinity of wafer surface layer after the RTP.Type: ApplicationFiled: May 14, 2010Publication date: November 18, 2010Inventors: Wataru Itou, Takashi Nakayama, Shigeru Umeno, Hiroaki Taguchi, Yasuo Koike
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Publication number: 20100288184Abstract: A method for manufacturing a silicon single crystal wafer for IGBT, including introducing a hydrogen atom-containing substance into an atmospheric gas at a hydrogen gas equivalent partial pressure of 40 to 400 Pa, and growing a single crystal having an interstitial oxygen concentration of 8.5×1017 atoms/cm3 or less at a silicon single crystal pulling speed enabling pulling of a silicon single crystal free of grown-in defects. The silicon single crystal is irradiated with neutrons so as to dope with phosphorous; an n-type dopant is added to the silicon melt; or phosphorous is added to the silicon melt so the phosphorous concentration in the silicon single crystal is 2.9×1013 to 2.9×1015 atoms/cm3; a p-type dopant having a segregation coefficient smaller than that of the phosphorous is added to the silicon melt so the concentration in the single crystal is 1×1013 to 1×1015 atoms/cm3 corresponding to the segregation coefficient thereof.Type: ApplicationFiled: July 30, 2010Publication date: November 18, 2010Inventors: Toshiaki ONO, Shigeru Umeno, Wataru Sugimura, Masataka Hourai
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Publication number: 20100111802Abstract: By determining a control direction of a pulling-up velocity without using a position or a width of an OSF region as an index, a subsequent pulling-up velocity profile is fed back and adjusted. A silicon single crystal ingot that does not include a COP and a dislocation cluster is grown by a CZ method, a silicon wafer is sliced from the silicon single crystal ingot, reactive ion etching is performed on the silicon wafer in an as-grown state, and a grown-in defect including silicon oxide is exposed as a protrusion on an etching surface. A growing condition in subsequent growing is fed back and adjusted on the basis of an exposed protrusion generation region. As a result, feedback with respect to a nearest batch can be performed without performing heat treatment to expose a defect.Type: ApplicationFiled: October 23, 2009Publication date: May 6, 2010Applicant: SUMCO CORPORATIONInventors: Shigeru UMENO, Keiichiro HIRAKI, Hiroaki TAGUCHI
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Publication number: 20100051945Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3 and with a diameter of a COP occurring region not more than a diameter of a crystal, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, and mirror polishing the other main surface of the wafer.Type: ApplicationFiled: August 20, 2009Publication date: March 4, 2010Applicant: SUMCO CORPORATIONInventors: Shigeru Umeno, Manabu Nishimoto, Masataka Hourai
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Publication number: 20100052103Abstract: A silicon wafer is produced through the steps of forming a silicon ingot by a CZ method with an interstitial oxygen concentration of not more than 7.0×1017 atoms/cm3, slicing a wafer from the silicon ingot after doping the silicon ingot with phosphorus, forming a polysilicon layer or a strained layer on one main surface of the wafer, mirror polishing the other main surface of the wafer, and performing a heat treatment for the wafer in a non-oxidizing atmosphere.Type: ApplicationFiled: August 20, 2009Publication date: March 4, 2010Applicant: SUMCO CORPORATIONInventors: Shigeru UMENO, Manabu NISHIMOTO, Masataka HOURAI