Abstract: A timing generating device, in which a period generator generates pulses the average period of which is equal to a preset period, at integral intervals of a reference clock period T, and provides fractional period data which indicates the phase difference between the above pulses and a pulse of the preset period for each of them. From a coarse delay circuit is yielded a pulse delayed behind the former pulse according to coarse delay data in a preset delay amount, which indicates a value greater than the reference clock period T. Fractional delay data in the preset delay amount which indicates a value smaller than the reference clock period, and the fractional period data are added together. By the added output the delayed pulses from the coarse delay circuit is delayed in a fine delay section by a value corresponding to the added value, thus producing a timing pulse.