Patents by Inventor Shigetaka Aoki
Shigetaka Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9570544Abstract: A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer.Type: GrantFiled: December 20, 2015Date of Patent: February 14, 2017Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Katsushige Yamashita, Kenichi Nishimura, Atsuya Yamamoto, Shigetaka Aoki
-
Patent number: 9406796Abstract: A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and performs bidirectional current control in a direction from a drain area to a source area and in a direction from the source area to the drain area. A sheet resistance of the back gate electrode is lower than a sheet resistance of the body area. The source area and the back gate electrode are disposed apart from each other with a clearance sufficient for preventing a breakdown phenomenon caused between the source area and the back gate electrode when a maximum operation voltage is applied between the source area and the drain area.Type: GrantFiled: December 15, 2015Date of Patent: August 2, 2016Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Katsushige Yamashita, Shigetaka Aoki
-
Publication number: 20160104795Abstract: A semiconductor device includes a second conductivity type back gate electrode formed within a body area, and electrically connected with the body area, and performs bidirectional current control in a direction from a drain area to a source area and in a direction from the source area to the drain area. A sheet resistance of the back gate electrode is lower than a sheet resistance of the body area. The source area and the back gate electrode are disposed apart from each other with a clearance sufficient for preventing a breakdown phenomenon caused between the source area and the back gate electrode when a maximum operation voltage is applied between the source area and the drain area.Type: ApplicationFiled: December 15, 2015Publication date: April 14, 2016Inventors: KATSUSHIGE YAMASHITA, SHIGETAKA AOKI
-
Publication number: 20160104767Abstract: A semiconductor device includes: a silicon substrate that includes a high-concentration layer containing first conductivity type impurities; a low-concentration layer formed on the high-concentration layer and containing first conductivity type impurities; a first electrode and a second electrode formed on the low-concentration layer; a vertical semiconductor element that allows current to flow between the second electrode and the high-concentration layer; and a first trench unit that realizes electric connection between the first electrode and the high-concentration layer. The first trench unit consists of first polysilicon containing first conductivity type impurities, and a diffusion layer configured to surround the first polysilicon in a plan view and to contain first conductivity type impurities. The first polysilicon is configured to reach the high-concentration layer by penetrating the low-concentration layer.Type: ApplicationFiled: December 20, 2015Publication date: April 14, 2016Inventors: KATSUSHIGE YAMASHITA, KENICHI NISHIMURA, ATSUYA YAMAMOTO, SHIGETAKA AOKI
-
Patent number: 7859030Abstract: A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the external base region are doped with a first impurity of a given conductivity type. The external base region is further doped with a second impurity. As the first impurity, an element smaller in atomic radius than Si (such as boron, for example) is selected, and as the second impurity, an element larger in atomic radius than the first impurity (such as Ge, In and Ga, for example) is selected.Type: GrantFiled: February 15, 2007Date of Patent: December 28, 2010Assignee: Panasonic CorporationInventor: Shigetaka Aoki
-
Publication number: 20090321880Abstract: A semicoductor device includes: a collector layer made of a first conductivity type semiconductor; an intrinsic base layer formed on the collector layer and including a second conductivity type monocrystalline silicon germanium layer; a base extraction electrode formed around the intrinsic base layer and including a second conductivity type polycrystalline silicon layer and a second conductivity type polycrystalline silicon germanium layer; and a first conductivity type emitter layer formed in an upper portion of the intrinsic base layer. A silicon layer is formed in the upper portion of the intrinsic base layer and the emitter layer includes an upper emitter region formed in an upper portion of the silicon layer and a lower emitter region formed below and in contact with the upper emitter region.Type: ApplicationFiled: February 24, 2009Publication date: December 31, 2009Inventor: Shigetaka Aoki
-
Patent number: 7579635Abstract: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.Type: GrantFiled: January 7, 2008Date of Patent: August 25, 2009Assignee: Panasonic CorporationInventor: Shigetaka Aoki
-
Publication number: 20080230808Abstract: A base layer made of SiGe mixed crystal includes a spacer layer formed in contact with a collector layer with no base impurities diffused therein and an intrinsic base layer formed in contact with an emitter layer with base impurities diffused therein. The spacer layer contains C at a low concentration. The intrinsic base layer has a first region containing C at a low concentration on the collector side and a second region containing C at a high concentration on the emitter side.Type: ApplicationFiled: January 7, 2008Publication date: September 25, 2008Inventor: Shigetaka Aoki
-
Publication number: 20070215979Abstract: A SiGe-HBT having a base region made of SiGe mixed crystal. The base region includes: an intrinsic base region having junctions with a collector region and an emitter region; and an external base region for connecting the intrinsic base region with a base electrode. The intrinsic base region and the external base region are doped with a first impurity of a given conductivity type. The external base region is further doped with a second impurity. As the first impurity, an element smaller in atomic radius than Si (such as boron, for example) is selected, and as the second impurity, an element larger in atomic radius than the first impurity (such as Ge, In and Ga, for example) is selected.Type: ApplicationFiled: February 15, 2007Publication date: September 20, 2007Inventor: Shigetaka Aoki
-
Patent number: 7109095Abstract: Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.Type: GrantFiled: March 26, 2003Date of Patent: September 19, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hidenori Notake, Teruhito Ohnishi, Akira Asai, Shigetaka Aoki
-
Publication number: 20060186437Abstract: A bipolar transistor, wherein a outgoing electrode is made of a polycrystalline Si film, and C atom, or Ge atom together with C atom are added in the polycrystalline Si film.Type: ApplicationFiled: February 15, 2006Publication date: August 24, 2006Inventor: Shigetaka Aoki
-
Patent number: 6919253Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.Type: GrantFiled: February 7, 2003Date of Patent: July 19, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
-
Publication number: 20050066887Abstract: A method of fabricating a semiconductor device according to the present invention includes a step A of forming a polycrystalline or amorphous preliminary semiconductor layer on a surface of a substrate so as to have an opening portion and a step B of simultaneously forming an epitaxial growth layer on an exposed portion of a surface of the substrate through the opening portion and a non-epitaxial growth layer on the preliminary semiconductor layer using a CVD method while heating the substrate inside a reaction chamber by means of a heat source inside the reaction chamber, the epitaxial growth layer being made of single crystalline semiconductor, and the non-epitaxial growth layer being comprised of a polycrystalline or amorphous semiconductor layer.Type: ApplicationFiled: February 7, 2003Publication date: March 31, 2005Inventors: Tohru Saitoh, Katsuya Nozawa, Minoru Kubo, Shigetaka Aoki
-
Publication number: 20040256635Abstract: In a hetero bipolar transistor according to the present invention, a SiGe spacer layer (40), a SiGe graded layer (41) having a portion functioning as a base layer and composed of a plurality of sublayers having different Ge composition ratios, and a Si cap layer (42) are formed on a collector layer (12) formed in a portion of a Si substrate (10). In the SiGe graded layer (41), when the thickness of each sublayer is larger, the number of sublayers is smaller, and difference in Ge composition ratio between adjacent sublayers is larger, measurement of the thickness of each sublayer becomes easier. However, in order to avoid degradation of a cut-off frequency characteristic of a device, the film thickness of each sublayer needs to be approximately 20 nm or less, and the number of sublayers is preferably 2 or more.Type: ApplicationFiled: October 22, 2003Publication date: December 23, 2004Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Tohru Saitoh, Shigetaka Aoki, Katsuya Nozawa, Teruhito Ohnishi
-
Publication number: 20040150004Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.Type: ApplicationFiled: February 2, 2004Publication date: August 5, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Shigetaka Aoki, Tohru Saitoh, Katsuya Nozawa
-
Patent number: 6762106Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.Type: GrantFiled: December 23, 2002Date of Patent: July 13, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shigetaka Aoki, Tohru Saitoh, Katsuya Nozawa
-
Patent number: 6717188Abstract: A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.Type: GrantFiled: February 8, 2002Date of Patent: April 6, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Shigetaka Aoki
-
Publication number: 20030186516Abstract: Immediately after a Si/SiGe film containing a contaminant is formed over all surfaces of a substrate by epitaxial growth, a portion of the Si/SiGe film formed to the back surface side of the substrate is removed by wet etching. In addition, the Si/SiGe film is subjected to processing with heating in a container, after which a dummy run is carried out in the container. These processings prevent secondary wafer contamination through a stage, a robot arm or a vacuum wand for handling a wafer and the contamination of the container also used in the fabrication process of a semiconductor device free from any group IV element but Si.Type: ApplicationFiled: March 26, 2003Publication date: October 2, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hidenori Notake, Teruhito Ohnishi, Akira Asai, Shigetaka Aoki
-
Publication number: 20030183819Abstract: An Si/SiGe layer including an Si buffer layer, an SiGe spacer layer, a graded SiGe layer and an Si cap layer is epitaxially grown in a region corresponding to a collector opening while a polycrystalline layer is deposited on the upper surface of a nitride film, and side surfaces of an oxide film and the nitride film. In this case, the Si buffer layer is formed first and then other layers such as the SiGe spacer layer are formed, thereby ensuring non-selective epitaxial growth. Then, a polycrystalline layer is deposited over the nitride film.Type: ApplicationFiled: December 23, 2002Publication date: October 2, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Shigetaka Aoki, Tohru Saitoh, Katsuya Nozawa
-
Publication number: 20020185656Abstract: A SiGe-HBT is provided with a SiGe film and a Si film grown in succession by epitaxial growth. The SiGe film is made up of a SiGe buffer layer, a SiGe graded composition layer, and a SiGe upper layer, in which the Ge content is substantially constant or changes not more than that of the SiGe graded composition layer. Even if there are fluctuations in the position of the EB junction, the EB junction is positioned in a portion of the SiGe upper layer, so fluctuations in the Ge content in the EB junction can be inhibited, and a stable high current amplification factor can be obtained. It is also possible to provide a SiGeC film instead of the SiGe film.Type: ApplicationFiled: February 8, 2002Publication date: December 12, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventor: Shigetaka Aoki