Patents by Inventor Shigetaka Kumashiro
Shigetaka Kumashiro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6931609Abstract: In order to calculate, at high precision, capacitance parameters of an equivalent circuit model including tunnel conductances corresponding to a film thickness of a gate oxide film of an MOSFET to make reliability of device evaluation and circuit simulation improve, a computer preliminarily stores an equivalent circuit model, converts S parameter data into Y parameter data, determines whether it is possible or impossible to calculate the capacitance parameters on the basis of a real part secondary dependent area and an imaginary part primary dependent area of a frequency characteristic of the Y parameter data, generates relational expressions for Y parameters of a two-terminal pair circuit that correspond to the equivalent circuit model, measurement conditions, and a manufacturing condition of the MOFET when it is possible to calculate the capacitance parameters, producing approximated expressions by approximation conditions corresponding to the real part secondary dependent area and the imaginary part primarType: GrantFiled: December 18, 2003Date of Patent: August 16, 2005Assignee: NEC Electronics CorporationInventors: Yasuhisa Naruta, Shigetaka Kumashiro
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Publication number: 20040133862Abstract: In order to calculate, at high precision, capacitance parameters of an equivalent circuit model including tunnel conductances corresponding to a film thickness of a gate oxide film of an MOSFET to make reliability of device evaluation and circuit simulation improve, a computer preliminarily stores an equivalent circuit model, converts S parameter data into Y parameter data, determines whether it is possible or impossible to calculate the capacitance parameters on the basis of a real part secondary dependent area and an imaginary part primary dependent area of a frequency characteristic of the Y parameter data, generates relational expressions for Y parameters of a two-terminal pair circuit that correspond to the equivalent circuit model, measurement conditions, and a manufacturing condition of the MOFET when it is possible to calculate the capacitance parameters, producing approximated expressions by approximation conditions corresponding to the real part secondary dependent area and the imaginary part primarType: ApplicationFiled: December 18, 2003Publication date: July 8, 2004Applicant: NEC Electronics CorporationInventors: Yasuhisa Naruta, Shigetaka Kumashiro
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Patent number: 6566695Abstract: In a MOSFET, a source region, a drain region and a channel region disposed between the source region and the drain region are provided. And the width W(x) of the channel region is changed according to the following mathematical equation.Type: GrantFiled: April 19, 2001Date of Patent: May 20, 2003Assignee: NEC Electronics CorporationInventor: Shigetaka Kumashiro
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Patent number: 6553340Abstract: In a computer simulation method for a semiconductor device, temporal changes in internal physical quantities such as electrostatic potential, electron density, and hole density in a semiconductor device upon application of a pulse voltage are obtained by transient analysis. AC signal analysis is performed by inputting a small RF AC voltage, assuming various physical quantities obtained at each time are in a pseudo steady state. The junction capacitance in the semiconductor device is calculated. These steps are repeatedly performed until a predetermined analysis time is reached to obtain transient temporal changes in junction capacitance.Type: GrantFiled: October 12, 2000Date of Patent: April 22, 2003Assignee: NEC Electronics CorporationInventor: Shigetaka Kumashiro
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Patent number: 6505147Abstract: A method for process simulation capable of simulating a segregation phenomenon of any impurity and a diffusion phenomenon for a system including a substance boundary such as an interface between a silicon layer and an oxide film. According to the method, accuracy of the simulation is maintained without use of a boundary protective layer. A diffusion equation is formulated by dividing a device model of the system into a mesh to form mesh points such that some of mesh points are disposed on the substance boundary, and treating each mesh point on the boundary as a multiple point of quadruplicated or higher. Thereupon, an interval between adjacent points among points constituting the multiple point is assumed to fall within a range of an effective distance of 0.3 nm or less, more preferably 0.1 nm or less, to formulate the diffusion equation.Type: GrantFiled: May 18, 1999Date of Patent: January 7, 2003Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 6426535Abstract: First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impurities are injected into a predetermined region in the first conductivity type region to selectively form a second conductivity type region. Then, first conductivity type impurities are selectively injected into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.Type: GrantFiled: October 4, 1999Date of Patent: July 30, 2002Assignee: NEC CorporationInventors: Kiyoshi Takeuchi, Shigetaka Kumashiro
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Publication number: 20020070413Abstract: First, first conductivity type impurities are injected into a semiconductor substrate to selectively form a first conductivity type region. Next, second conductivity type impurities higher in concentration than that of the first conductivity type impurities are injected into a predetermined region in the first conductivity type region to selectively form a second conductivity type region. Then, first conductivity type impurities are selectively injected into the second conductivity type region to selectively form a lightly doped second conductivity type region. By the step, a concentration distribution is formed in which a concentration of first conductivity type impurities increases from the first conductivity type region toward the lightly doped second conductivity type region.Type: ApplicationFiled: October 4, 1999Publication date: June 13, 2002Inventors: KIYOSHI TAKEUCHI, SHIGETAKA KUMASHIRO
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Patent number: 6360190Abstract: In this semiconductor process device simulation method, a coefficient matrix constituted by a principal diagonal submatrix arranged at any one of principal diagonals corresponding to each mesh point and representing a self feedback function at the mesh point, the principal diagonal submatrix having rows and columns in numbers corresponding to the number of mesh points, and a non-principal diagonal submatrix arranged on any one of a row and column passing through principal diagonal positions corresponding to the mesh point and representing an interaction between the mesh point corresponding to the principal diagonal positions and an adjacent mesh point connected to the mesh point through a mesh branch is generated. Calculation for the submatrices is performed while regarding each submatrix of the coefficient matrix as one element, thereby performing incomplete LU factorization of the coefficient matrix.Type: GrantFiled: November 25, 1998Date of Patent: March 19, 2002Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Publication number: 20010038134Abstract: In a MOSFET, a source region, a drain region and a channel region disposed between the source region and the drain region are provided. And the width W(x) of the channel region is changed according to the following mathematical equation.Type: ApplicationFiled: April 19, 2001Publication date: November 8, 2001Applicant: NEC CorporationInventor: Shigetaka Kumashiro
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Publication number: 20010002707Abstract: A MOSFET simulation apparatus includes an output unit, and a processor which simulates an operation of MOSFET using a new MOSFET model, and outputs the simulation result to the output unit. The new MOSFET model includes a MOSFET model, a first circuit model and a second circuit model. The MOSFET model is known as BSIM3V3 and has a gate, a source, a drain and a gate insulating film. The first circuit model is connected between the gate and the source, and includes first and second diode models connected in parallel in opposite directions to each other. The second circuit model connected between the gate and the drain, and including third and fourth diode models connected in parallel in opposite directions to each other.Type: ApplicationFiled: November 30, 2000Publication date: June 7, 2001Inventor: Shigetaka Kumashiro
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Patent number: 6242272Abstract: In a reverse profiling method, first and second processes produce first and second groups of MOSFETs, respectively. In the first process, channel impurities are implanted into a semiconductor substrate after implantation of source/drain impurities and annealing of the semiconductor substrate. Consequently, the annealing modulates channel impurity density distribution. On the other hand, in the second process, source/drain impurities are implanted into a semiconductor substrate after implantation of channel impurities and annealing of the semiconductor substrate. The annealing does not modulate channel impurity density distribution in the second process. First threshold voltage-gate length characteristics of the MOSFETs of the first group are found. Similarly, second threshold voltage-gate length characteristics of the MOSFETs of the first group are found.Type: GrantFiled: August 2, 1999Date of Patent: June 5, 2001Assignee: NEC CorporationInventors: Shigetaka Kumashiro, Kiyoshi Takeuchi
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Patent number: 6154717Abstract: A simulation method is provided, which makes it possible to simulate diffusion of doped impurity in Si and SiO.sub.2 in consideration of the pileup phenomenon of the doped impurity without using any intermediate layer. In the step (a), a mesh having mesh points is configured on a simulated zone including a SiO.sub.2 region and a Si region contracted therewith, thereby partitioning the simulated zone into domains. A first one of the mesh points is located in a SiO.sub.2 region. A second one of the mesh points is located in a Si region. A third one of the mesh points is located at an interface of the SiO.sub.2 and Si regions. The third one of the mesh points serves as a double mesh point having first and second impurity concentrations. The first impurity concentration represents a general impurity concentration of a first one of the domains located in the SiO.sub.2 region and adjacent to the interface of the SiO.sub.2 and Si regions.Type: GrantFiled: November 9, 1998Date of Patent: November 28, 2000Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 6144929Abstract: A method of simulating an impact ionization phenomenon of a semiconductor device, by which an electric characteristic concerning the impact ionization phenomenon of the semiconductor device is obtained by setting a mesh in a space and by solving a Poisson equation, an electron current continuity equation and a hole current continuity equation which are discretized by what is called a control volume method. Further, regarding a current density defined on a mesh edge connecting adjacent mesh points, different values are used as an evaluation value of the current density at an upstream side, at which a carrier is cased to drift, and an evaluation value of the current density at a downstream side, respectively.Type: GrantFiled: August 20, 1998Date of Patent: November 7, 2000Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 6080200Abstract: A total impurity concentration which is a result of the solution of a diffusion equation at the immediately preceding point of time is used to solve, for each mesh point, an equation for determining an electrically active impurity concentration to approximately determine an electrically active impurity concentration. A ratio between the approximate value of the electrically active impurity concentration and the total concentration of the impurities at the preceding point of time is determined for each mesh point. A value of the ratio is determined by interpolating values at mesh points at the opposite ends of each mesh branch. A diffusion equation which includes the total concentration of the impurities as a variable and employs an effective diffusion constant is solved to determine a total impurity concentration at the present point of time of analysis.Type: GrantFiled: October 27, 1998Date of Patent: June 27, 2000Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 6006026Abstract: A method for simulating a concentration of impurities within a semiconductor device while the semiconductor device is being oxidized includes setting a transition region in a part of the semiconductor device which is oxidized for a unit time period, and then calculating the concentration of impurities within the transition region by solving a diffusion equation using an impurity diffusion coefficient peculiar to the transition region, thus obtaining a redistribution of impurities within the transition region.Type: GrantFiled: August 21, 1997Date of Patent: December 21, 1999Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 5847973Abstract: High-speed simulation of oxidation is performed even when an overlap occurs between oxide-film shapes. A sweeping quadrilateral is defined accompanying the growth of an oxide film from a line segment composing the surface of the oxide film before the growth, the line segment on the surface of an oxide film after the growth and the dislocation vectors of both ends in these segments. The overlap width of the oxide-film shapes is then acquired by a predetermined figure calculation of these sweeping quadrilaterals between them. A linear estimation is made on the time axis when an overlap between the oxide-film shapes occurs. The growth time of the oxide film is retrogressed so that the overlap width of said oxide-film shapes decreases below a previously specified allowable value. Thereafter, the oxidation simulation is continued with this state made into a renewed initial state.Type: GrantFiled: January 16, 1997Date of Patent: December 8, 1998Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 5784302Abstract: In an interstitial concentration simulating method, a mesh is set in a simulation region of a semiconductor device. Under a condition that an area outside of the simulation region is infinite, a provisional interstitial concentration and a provisional interstitial diffusion flux at the boundary of the simulation region are calculated. Then, an interstitial diffusion rate at the boundary of the simulation region is calculated by a ratio of the provisional interstitial diffusion flux to the provisional interstitial concentration. Finally, an interstitial diffusion equation is solved for each element of the mesh using the interstitial diffusion rate at the boundary.Type: GrantFiled: March 12, 1996Date of Patent: July 21, 1998Assignee: NEC CorporationInventor: Shigetaka Kumashiro
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Patent number: 5682338Abstract: In order to estimate an initial potential value for semiconductor device simulation at each of iterative procedures a computer system, a plurality of bias conditions are stored in a memory. Following this, one bias condition is retrieved from the memory at a given iterative procedure. Further, an analysis result already obtained in an iterative procedure, which precedes the given iterative procedure, is retrieved from the memory. Subsequently, an initial potential value is estimated which is used in the give iterative procedure by solving a Laplace equation which is weighted by a coefficient including a reciprocal of electric field intensity.Type: GrantFiled: September 11, 1995Date of Patent: October 28, 1997Assignee: NEC CorporationInventors: Ikuhiro Yokota, Shigetaka Kumashiro
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Patent number: 5677846Abstract: A device simulator including a boundary protection layer generation portion for generating a boundary protection layer which will not cause parasitic resistance in the vicinity of a boundary between different components of a semiconductor device whose electric characteristics is to be simulated, a mesh point generation portion for allocating a mesh point apart from the boundary protection layer by a predetermined reference distance, and a mesh generation portion for generating a triangular mesh by connecting the mesh point.Type: GrantFiled: December 9, 1994Date of Patent: October 14, 1997Assignee: NEC CorporationInventor: Shigetaka Kumashiro