Patents by Inventor Shigetaka Onishi

Shigetaka Onishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Manufacturing method of semiconductor device
    Patent number: 8039364
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: October 18, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi
  • Manufacturing method of semiconductor device
    Publication number: 20100207252
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Application
    Filed: April 23, 2010
    Publication date: August 19, 2010
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi
  • Manufacturing method of semiconductor device
    Patent number: 7736999
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 15, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi
  • Manufacturing method of semiconductor device
    Publication number: 20070218586
    Abstract: An adhesive layer of which thickness is over 25 ?m and a dicing tape are laminated on a rear surface of a semiconductor wafer. The semiconductor wafer is cut together with a part of the adhesive layer by using a first blade of which cutting depth reaches the adhesive layer. The adhesive layer is cut together with a part of the dicing tape by using a second blade of which cutting depth reaches the dicing tape and of which width is narrower than the first blade. A semiconductor element sectioned by cutting the semiconductor wafer with the adhesive layer is picked up from the dicing tape, and is adhered on another semiconductor element or a circuit board.
    Type: Application
    Filed: March 9, 2007
    Publication date: September 20, 2007
    Inventors: Atsushi Yoshimura, Tadanobu Okubo, Shigetaka Onishi