Patents by Inventor Shigetaka Takagi

Shigetaka Takagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8046402
    Abstract: A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights ki (i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l1 (i=1 to 4), and adding the divided signals Vout1 to Vout4 weighted by the second weights. The first weights are k1=t, k2=?t, k3=1, k4=?1, while the second weights are l1=?1, l2=1, l3=t3, l4=?t3. Here, t=b/a (where a and b are different positive integers).
    Type: Grant
    Filed: June 18, 2007
    Date of Patent: October 25, 2011
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Shigetaka Takagi, Yosuke Sakai, Tetsuro Itakura, Koichiro Mashiko
  • Publication number: 20090102545
    Abstract: An input signal (Vin) is divided into n (?3) number of divided signals which are weighted by first weights (ki). The weighted divided signals are processed by n number of signal processing means 1 to n performing the same signal processing. The processed divided signals are weighted by second weights (li) and added to obtain an output signal (Vout). By selecting the first weights (ki) and the second weights (li), it is possible to eliminate noise or eliminate distortion.
    Type: Application
    Filed: April 25, 2006
    Publication date: April 23, 2009
    Inventors: Shigetaka Takagi, Nobuo Fujii, Takahide Sato, Kazuyuki Wada
  • Publication number: 20080100366
    Abstract: A signal processing method and apparatus reducing distortion using divided signals differing in only amplitude by weighting an input signal by first weights ki (i=1 to 4) to obtain divided signals, performing the same signal processing f(x) on the divided signals, weighting the signal processed divided signals by second weights l1 (i=1 to 4), and adding the divided signals Vout1 to Vout4 weighted by the second weights. The first weights are k1=t, k2=?t, k3=1, k4=?1, while the second weights are l1=?1, l2=1, l3=t3, l4=?t3. Here, t=b/a (where a and b are different positive integers).
    Type: Application
    Filed: June 18, 2007
    Publication date: May 1, 2008
    Applicant: SEMICONDUCTOR TECHNOLOGY ACADEMIC RESEARCH CENTER
    Inventors: Shigetaka Takagi, Yosuke Sakai, Tetsuro Itakura, Koichiro Mashiko
  • Patent number: 6664854
    Abstract: When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circuits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: December 16, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Tanaka, Shigetaka Takagi, Nobuo Fujii
  • Publication number: 20030052738
    Abstract: When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circuits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 20, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Satoshi Tanaka, Shigetaka Takagi, Nobuo Fujii
  • Patent number: 6476676
    Abstract: When an input signal to be amplified is very small and a large blocking signal having a high frequency is included in an input, it is necessary for a filter for mobile communication for removing thereof that a common-mode signal rejection ratio is large. Further, even in the case of an amplifier having a high gain, it is preferable that the common-mode rejection ratio is large in order to avoid saturation of the amplifier by noise. A common-mode rejecting characteristic is added to an input stage by making transconductance circuits of an input of an integrating circuit proposed by Nauta differential circits and connecting thereof in cross connection. Thereby, a filter as well as an amplifier improving the common-mode rejection ratio of a total, are realized by being applied to a CMOS process or a BiCMOS process.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: November 5, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Satoshi Tanaka, Shigetaka Takagi, Nobuo Fujii
  • Patent number: 6388520
    Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: May 14, 2002
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii
  • Publication number: 20010005163
    Abstract: A semiconductor integrated circuit comprises an amplifier circuit including a current output amplifier, a load resistor having one end connected to an output terminal of the current output amplifier and a voltage control circuit having an input terminal connected to the one end of the load resistor and an output terminal connected to an other end of the load resistor. The input terminal of the amplifier circuit serves as an input terminal of the current output amplifier, and the output terminals of the amplifier circuit serve as the individual ends of the load resistor.
    Type: Application
    Filed: December 19, 2000
    Publication date: June 28, 2001
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Kazuyuki Wada, Shigetaka Takagi, Nobuo Fujii