Abstract: A data processor includes a central processing unit having an execution unit, a program counter for supplying the address of the instruction to be executed and a program status word for holding the execution status of the program, an interrupt request generating means for generating the processing request in asynchronisum with the central processing unit, and interrupt controller receiving the processing request from the interrupt requested generating means and a data memory for storing the processing data. The interrupt request generating means is capable of generating a macro-service request for starting the macro-service processing while saving the contents of the program counter and the program status word. The data memory the control information for starting the macro-service processing and the command information for executing a plurality of macro-service processing. The control information includes a base address for the command information corresponding to the macro-service processing.

Abstract: A queue apparatus comprises a multi-stage queue latch for storing instruction codes or data in a first-in first-out manner; a first queue pointer associated with the queue latch for indicating a read position of an upper half place portion of the instruction codes or data stored in the queue latch and a second queue pointer associated with the queue latch for indicating a reading position of a lower half place portion of the instruction codes or data stored in the queue latch. An exchanger is coupled in order to the queue latch to receive the upper and lower half place portions of the instruction codes or data read out form the queue latch and for selectively exchanging the positions of the received upper and lower half place portions.

Abstract: An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs and interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

Abstract: An information processor has at least one interface unit by which the processor is coupled to a peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart a program execution which is stopped by the interruption to a stack memory is performed before start of the interruption operation. While the processor can perform the interruption operation in response to the second mode signal without the stack operation, whereby an improved processor with less overhead can be provided.

Abstract: An information processor has at least one interface unit by which the processor is coupled to peripheral equipment. The interface unit can selectively generate either a first mode signal or a second mode signal when the processor performs an interruption operation according to request from the peripheral equipment. When the processor performs the interruption operation in response to the first mode signal, a stack operation for saving information necessary to restart execution of a program which is stopped by the interruption in a stack memory is performed before the start of the interruption operation. The processor can perform the interruption operation in response to the second mode signal without the stack operation, providing an improved processor with less overhead. The two interruption mode technique is described in a number of applications, including D/A conversion, serial data transmission and reception, and operation of computer peripheral devices.

Abstract: Herein disclosed is a serial data transfer system which has first and second serial data processors connected via a single data line and a single clock line for transferring serial data therebetween. Each of the first and second serial data processors includes: reception confirmation signal output means for outputting a reception confirmation signal to the data line; and reception confirmation signal detection means for detecting the reception confirmation signal on the data line. The confirmation of the data transfer is executed in synchronism with serial clock pulses outputted to the clock line. Alternatively, the first or second serial data processor includes: an output circuit for outputting a reception confirmation signal to the data line; a circuit for generating a first signal indicating the end of reception of the serial data; a circuit for generating a second signal indicating the end of processing of the data received; and a circuit for controlling the output of said reception confirmation signal.

Abstract: A microcomputer comprises a microprocessor chip and a memory chip coupled to each other. The memory chip includes a memory for storing various processing data, a bus interface for designating an address information of the memory to be accessed for a data transfer, and an address latch for temporarily holding the address information from the bus interface and so as to supply the address information to the memory. Furthermore, there is provided an automatically updated data pointer whose initial value is set with the address information supplied from the bus interface. In case of individually designating an address for each item of data to be transferred, the address latch is used to supply the address information to the memory so that an address is given to the address latch by the bus interface for each data transfer of one unitary data.

Abstract: A serial data communication system is disclosed. This system includes a plurality of stations which are interconnected by a single clock wire and a single data wire. A master station in the stations includes a transistor push-pull circuit for driving the clock wire to output a clock signal on the clock wire. The clock signal thus has sharp leading and falling edges. The data wire is coupled to wire logic means. A transmitting station transmits each bit of a data signal on the data wire in synchronism with one of leading and falling edges of the associated clock pulse of the clock signal, and a receiving station receives each bit of the data signal in synchronism with the other of leading and falling edges of the associated clock pulse.

Abstract: A microprocessor includes a central processing unit which executes a program according to at least one control signal generated by an instruction decoder. The instruction decoder is designed such that a first type instruction compatible for the central processing unit can be decoded. A second type instruction not compatible for the central processing unit is applied as an address to a conversion memory in which a first type instruction corresponding in function to the second type instruction has been stored. The first type instruction in the conversion memory is then applied to the instruction decoder instead of the second type instruction. Thus, the second type instruction can be executed by the central processing unit which is not otherwise compatible with the second type instruction.