Patents by Inventor Shigeto Fukatsu
Shigeto Fukatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11728386Abstract: A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.Type: GrantFiled: July 14, 2021Date of Patent: August 15, 2023Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hiroshi Kono, Souzou Kanie, Shigeto Fukatsu, Takuma Suzuki
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Publication number: 20230084127Abstract: A semiconductor device manufacturing method of embodiments includes: forming a silicon oxide film on a surface of a silicon carbide layer; performing a first heat treatment in an atmosphere containing nitrogen gas at a temperature equal to or more than 1200° C. and equal to or less than 1600° C.; and performing a second heat treatment in an atmosphere containing nitrogen oxide gas at a temperature equal to or more than 750° C. and equal to or less than 1050° C.Type: ApplicationFiled: March 7, 2022Publication date: March 16, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tatsuo SHIMIZU, Yukio NAKABAYASHI, Toshihide ITO, Chiharu OTA, Shigeto FUKATSU, Johji NISHIO, Ryosuke IIJIMA
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Publication number: 20230064865Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include preparing a structure body, the structure body including a silicon carbide member and a first film stacked with the silicon carbide member. The first film includes silicon and oxygen. The method can include performing a first treatment of heat-treating the structure body in a first atmosphere including hydrogen. The method can include, after the first treatment, performing a second treatment of heat-treating the structure body in a second atmosphere including nitrogen and oxygen. An oxygen concentration in the second atmosphere is not less than 5 ppm and not more than 1000 ppm.Type: ApplicationFiled: August 2, 2022Publication date: March 2, 2023Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Shigeto FUKATSU, Yukio NAKABAYASHI, Tatsuo SHIMIZU, Ryosuke IIJIMA
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Publication number: 20210343842Abstract: A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Hiroshi Kono, Souzou Kanie, Shigeto Fukatsu, Takuma Suzuki
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Patent number: 11094786Abstract: A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.Type: GrantFiled: March 4, 2020Date of Patent: August 17, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Hiroshi Kono, Souzou Kanie, Shigeto Fukatsu, Takuma Suzuki
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Publication number: 20210091186Abstract: A semiconductor device of embodiments includes a silicon carbide layer including an element region and a termination region around the element region, the termination region having first straight-line portions extending in a first direction, second straight-line portions extending in a second direction, and corner portions between the first straight-line portions and the second straight-line portions, the termination region including a second-conductivity-type second silicon carbide region having a dot-line shape with first dot portions and first space portions surrounding the element region, an occupation ratio of the first dot portions is larger in the corner portions than in the first straight-line portions, and a second-conductivity-type third silicon carbide region having a dot-line shape with second dot portions and second space portions surrounding the second silicon carbide region, an occupation ratio of the second dot portions is lager in the corner portions than in the first straight-line portions.Type: ApplicationFiled: March 4, 2020Publication date: March 25, 2021Inventors: Hiroshi Kono, Souzou Kanie, Shigeto Fukatsu, Takuma Suzuki
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Patent number: 10892332Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.Type: GrantFiled: September 3, 2019Date of Patent: January 12, 2021Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage CorporationInventors: Shigeto Fukatsu, Masaru Furukawa, Hiroshi Kono, Takuma Suzuki, Shunsuke Asaba
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Publication number: 20200295140Abstract: A semiconductor device according to an embodiment includes a silicon carbide layer; a gate electrode; and a gate insulating layer which is provided between the silicon carbide layer and the gate electrode and includes a first silicon oxide layer and a second silicon oxide layer provided between the first silicon oxide layer and the gate electrode, the first silicon oxide layer having a first nitrogen concentration and a first thickness, the second silicon oxide layer having a second nitrogen concentration lower than the first nitrogen concentration and a second thickness. The second thickness between an end portion of the gate electrode and the silicon carbide layer is greater than the second thickness between a central portion of the gate electrode and the silicon carbide layer.Type: ApplicationFiled: September 3, 2019Publication date: September 17, 2020Inventors: Shigeto Fukatsu, Masaru Furukawa, Hiroshi Kono, Takuma Suzuki, Shunsuke Asaba
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Patent number: 10741395Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.Type: GrantFiled: February 12, 2018Date of Patent: August 11, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Shunsuke Asaba, Ryosuke Iijima, Yukio Nakabayashi, Shigeto Fukatsu, Toshihide Ito
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Patent number: 10714610Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).Type: GrantFiled: August 27, 2018Date of Patent: July 14, 2020Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Ryosuke Iijima, Toshihide Ito, Shunsuke Asaba, Yukio Nakabayashi, Shigeto Fukatsu
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Publication number: 20190296146Abstract: A semiconductor device of an embodiment includes a silicon carbide layer; a gate electrode; a gate insulating layer disposed between the silicon carbide layer and the gate electrode; a first region disposed in the silicon carbide layer and containing nitrogen (N); and a second region disposed between the first region and the gate insulating layer, and containing at least one element selected from the group consisting of nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), scandium (Sc), yttrium (Y), lanthanum (La), lanthanoids (Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu), hydrogen (H), deuterium (D), and fluorine (F).Type: ApplicationFiled: August 27, 2018Publication date: September 26, 2019Applicant: Kabushiki Kaisha ToshibaInventors: Tatsuo SHIMIZU, Ryosuke IIJIMA, Toshihide ITO, Shunsuke ASABA, Yukio NAKABAYASHI, Shigeto FUKATSU
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Patent number: 10373833Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.Type: GrantFiled: February 29, 2016Date of Patent: August 6, 2019Assignee: Kabushiki Kaisha ToshibaInventors: Aya Shindome, Masahiko Kuraguchi, Hisashi Saito, Shigeto Fukatsu, Miki Yumoto, Yosuke Kajiwara
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Publication number: 20180330949Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method can include performing a first heat treatment of a first film at a first temperature not less than 500° C. and not more than 900° C. in a first atmosphere including oxygen. The first film includes silicon and oxygen and is deposited on a semiconductor member including silicon carbide. The method can include performing, after the first heat treatment, a second heat treatment of the first film at a second temperature not less than 1200° C. but less than 1400° C. in a second atmosphere including nitrogen.Type: ApplicationFiled: February 12, 2018Publication date: November 15, 2018Applicant: Kabushiki Kaisha ToshibaInventors: Shunsuke ASABA, Ryosuke IIJIMA, Yukio NAKABAYASHI, Shigeto FUKATSU, Toshihide ITO
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Publication number: 20160284831Abstract: A semiconductor device of an embodiment includes a first GaN-based semiconductor layer, a second GaN-based semiconductor layer provided on the first GaN-based semiconductor layer and having a larger bandgap than the first GaN-based semiconductor layer, a source electrode provided on the second GaN-based semiconductor layer, a drain electrode provided on the second GaN-based semiconductor layer, a recess provided between the source electrode and the drain electrode in the second GaN-based semiconductor layer, a gate insulating film provided on a surface of the recess, and a gate electrode provided on the gate insulating film and having an end portion in a gate width direction, located in the recess.Type: ApplicationFiled: February 29, 2016Publication date: September 29, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Aya SHINDOME, Masahiko KURAGUCHI, Hisashi SAITO, Shigeto FUKATSU, Miki YUMOTO, Yosuke KAJIWARA
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Patent number: 9196822Abstract: A magnetoresistive effect element in one or more embodiments of the present invention is provided with a memory layer with a variable magnetization direction having a magnetic anisotropy in a direction perpendicular to a film surface, a reference layer with an invariable magnetization direction having the magnetic anisotropy in a direction perpendicular to the film surface, and a tunnel barrier layer formed between the memory layer and the reference layer. The tunnel barrier layer has a first portion at the central part in the film surface and a second portion at a peripheral part. The second portion contains at least boron and oxygen.Type: GrantFiled: February 26, 2013Date of Patent: November 24, 2015Assignee: Kabushiki Kaisha ToshibaInventors: Shigeto Fukatsu, Tatsuya Kishi, Masahiko Nakayama, Akiyuki Murayama
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Publication number: 20140070343Abstract: A magnetoresistive effect element in one or more embodiments of the present invention is provided with a memory layer with a variable magnetization direction having a magnetic anisotropy in a direction perpendicular to a film surface, a reference layer with an invariable magnetization direction having the magnetic anisotropy in a direction perpendicular to the film surface, and a tunnel barrier layer formed between the memory layer and the reference layer. The tunnel barrier layer has a first portion at the central part in the film surface and a second portion at a peripheral part. The second portion contains at least boron and oxygen.Type: ApplicationFiled: February 26, 2013Publication date: March 13, 2014Applicant: Kabushiki Kaisha ToshibaInventors: Shigeto FUKATSU, Tatsuya KISHI, Masahiko NAKAYAMA, Akiyuki MURAYAMA
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Patent number: 8665639Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a perpendicular and variable magnetization, a second magnetic layer with a perpendicular and invariable magnetization, and a first nonmagnetic layer between the first and second magnetic layer. The first magnetic layer has a laminated structure of first and second ferromagnetic materials. A magnetization direction of the first magnetic layer is changed by a current which pass through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer. A perpendicular magnetic anisotropy of the second ferromagnetic material is smaller than that of the first ferromagnetic material. A film thickness of the first ferromagnetic material is thinner than that of the second ferromagnetic material.Type: GrantFiled: February 28, 2012Date of Patent: March 4, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Toshihiko Nagase, Tadashi Kai, Katsuya Nishiyama, Eiji Kitagawa, Tadaomi Daibou, Masahiko Nakayama, Makoto Nagamine, Shigeto Fukatsu, Masatoshi Yoshikawa, Hiroaki Yoda
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Patent number: 8476718Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm?3 to 2.96×1020 cm?3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.Type: GrantFiled: February 23, 2010Date of Patent: July 2, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Izumi Hirano, Yuichiro Mitani, Tatsuo Shimizu, Yasushi Nakasaki, Akiko Masada, Shigeto Fukatsu, Masahiro Koike
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Publication number: 20120163070Abstract: According to one embodiment, a magnetoresistive element includes a first magnetic layer with a perpendicular and variable magnetization, a second magnetic layer with a perpendicular and invariable magnetization, and a first nonmagnetic layer between the first and second magnetic layer. The first magnetic layer has a laminated structure of first and second ferromagnetic materials. A magnetization direction of the first magnetic layer is changed by a current which pass through the first magnetic layer, the first nonmagnetic layer and the second magnetic layer. A perpendicular magnetic anisotropy of the second ferromagnetic material is smaller than that of the first ferromagnetic material. A film thickness of the first ferromagnetic material is thinner than that of the second ferromagnetic material.Type: ApplicationFiled: February 28, 2012Publication date: June 28, 2012Inventors: Toshihiko Nagase, Tadashi Kai, Katsuya Nishiyama, Eiji Kitagawa, Tadaomi Daibou, Masahiko Nakayama, Makoto Nagamine, Shigeto Fukatsu, Masatoshi Yoshikawa, Hiroaki Yoda
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Publication number: 20100244157Abstract: A semiconductor device includes a MISFET comprising: a semiconductor layer including a semiconductor region formed therein; a gate insulating film formed above the semiconductor region, and including a metal oxide layer containing a metal and oxygen, the metal contained in the metal oxide layer being at least one selected from Hf and Zr, the metal oxide layer further including at least one element selected from the group consisting of Ru, Cr, Os, V, Tc, and Nb, the metal oxide layer having sites that capture or release charges formed by inclusion of the element, density of the element in the metal oxide layer being in the range of 1×1015 cm?3 to 2.96×1020 cm?3, the sites being distributed to have a peak closer to the semiconductor region than to a center of the metal oxide layer; and a gate electrode formed on the gate insulating film.Type: ApplicationFiled: February 23, 2010Publication date: September 30, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Izumi HIRANO, Yuichiro Mitani, Tatsuo Shimizu, Yasushi Nakasaki, Akiko Masada, Shigeto Fukatsu, Masahiro Koike