Patents by Inventor Shigeto Honda
Shigeto Honda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240055306Abstract: The following steps (a) to (d) are provided. The step (a) is to form a drift layer of an n type on a silicon carbide semiconductor substrate of the n type through epitaxial growth. The step (b) is to measure impurity concentration of the drift layer. The step (c) is to form an ion implantation mask on the drift layer, the ion implantation mask including a plurality of first openings being periodically provided. The step (d) is to implant impurity ions of a p type through the plurality of first openings, form a plurality of second pillar regions of the p type in the drift layer, and turn the drift layer between the plurality of second pillar regions into a first pillar region. The step (d) includes performing feedforward control on an ion implantation amount so that there is a positive correlation with measurement results of the step (b).Type: ApplicationFiled: June 6, 2023Publication date: February 15, 2024Applicant: Mitsubishi Electric CorporationInventors: Yuichi NAGAHISA, Shigeto HONDA, Shinya AKAO, Shigehisa YAMAMOTO
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Publication number: 20230387278Abstract: According to the present disclosure, a semiconductor apparatus comprises a first gate electrode; a second gate electrode connected in parallel with the first gate electrode; a control circuit connected to the first gate electrode and the second gate electrode and configured to control gate voltages; and a coil connected between the second gate electrode and the control circuit.Type: ApplicationFiled: December 7, 2022Publication date: November 30, 2023Applicant: Mitsubishi Electric CorporationInventors: Yuji EBIIKE, Shigeto Honda
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Publication number: 20230261056Abstract: To suppress an increase in RC-IGBT recovery loss. In a semiconductor device, an IGBT region includes a base layer of a second conductivity type in a surface layer of a drift layer, a diode region includes an anode layer of a second conductivity type in the surface layer of the drift layer, a termination region includes a well layer of the second conductivity type in the surface layer of the drift layer, an impurity concentration profile of the base layer and an impurity concentration profile of the anode layer in a direction along an upper surface of the drift layer cyclically fluctuate, and the impurity concentration profile of the base layer and the impurity concentration profile of the anode layer are different.Type: ApplicationFiled: November 1, 2022Publication date: August 17, 2023Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Yusuke FUKADA, Hayato OKAMOTO
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Patent number: 11715789Abstract: A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.Type: GrantFiled: July 12, 2021Date of Patent: August 1, 2023Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Takahashi, Hidenori Fujii, Shigeto Honda
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Publication number: 20230131163Abstract: A semiconductor device includes a first electrode and a second electrode. The first electrode is connected to a collector layer and a first portion on the collector layer side of a cathode layer. The second electrode is connected to a second portion of the cathode layer excluding the first portion. A work function of the first electrode is larger than a work function of the second electrode, and one of the first electrode and the second electrode and the semiconductor substrate sandwich another of the first electrode and the second electrode in a thickness direction of the semiconductor substrate.Type: ApplicationFiled: August 15, 2022Publication date: April 27, 2023Applicant: Mitsubishi Electric CorporationInventors: Koichi NISHI, Koji TANAKA, Shinya SONEDA, Shigeto HONDA, Naoyuki TAKEDA
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Patent number: 11575001Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.Type: GrantFiled: July 12, 2021Date of Patent: February 7, 2023Assignee: Mitsubishi Electric CorporationInventors: Tetsuo Takahashi, Hidenori Fujii, Shigeto Honda
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Patent number: 11569225Abstract: A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.Type: GrantFiled: March 10, 2021Date of Patent: January 31, 2023Assignee: Mitsubishi Electric CorporationInventors: Shigeto Honda, Takahiro Nakatani, Tetsuya Nitta
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Publication number: 20220157809Abstract: According to an aspect of the present disclosure, a semiconductor device includes a FWD region that has, on an upper surface side of a substrate, a p-type anode region, a first p-type contact region having a higher p-type impurity concentration than the p-type anode region, and a first trench, and an IGBT region that surrounds the FWD region in plan view via a boundary region, and has an n-type emitter region, a second p-type contact region, and a second trench on the upper surface side of the substrate, wherein the first trench is formed annularly along an outer edge of the FWD region in plan view, the second trench is formed annularly along an outer edge of the boundary region in plan view, and only a p-type region is provided on an upper surface side of the boundary region.Type: ApplicationFiled: April 9, 2021Publication date: May 19, 2022Applicant: Mitsubishi Electric CorporationInventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
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Publication number: 20220109063Abstract: A transistor and a diode are formed on a common semiconductor substrate; the semiconductor substrate has a transistor region and an outer peripheral region surrounding it; the transistor region is divided into a plurality of channel regions and a plurality of non-channel regions by a plurality of gate electrodes each having a stripe shape; each of the plurality of non-channel regions has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fifth semiconductor layer, a first electrode, and a second electrode; the third semiconductor layer and the fifth semiconductor layer are electrically connected to the second electrode via a contact hole; and the fifth semiconductor layer is selectively provided not to be in contact with an impurity layer of a first conductivity type that is provided in the outer peripheral region and defines a boundary with a cell region.Type: ApplicationFiled: July 12, 2021Publication date: April 7, 2022Applicant: Mitsubishi Electric CorporationInventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
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Publication number: 20220109044Abstract: A semiconductor substrate has a transistor region, a diode region, and an outer peripheral region. The transistor region is divided into a plurality of transistor unit cell regions by a plurality of gate electrodes each having a stripe shape, and the diode region is divided into a plurality of diode unit cell regions by the plurality of gate electrodes. Each of the plurality of transistor unit cell regions has a third semiconductor layer of a first conductivity type provided on a first main surface side of the semiconductor substrate, a fourth semiconductor layer of a second conductivity type selectively provided on an upper layer part of the third semiconductor layer, and a fifth semiconductor layer. The fifth semiconductor layer is provided to be in contact with an impurity layer of the first conductivity type provided in the outer peripheral region, or to enter the impurity layer.Type: ApplicationFiled: July 12, 2021Publication date: April 7, 2022Applicant: Mitsubishi Electric CorporationInventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
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Publication number: 20220084825Abstract: There is provided a reverse-conducting IGBT having an improved trade-off relationship between recovery losses and a forward voltage drop during diode operation. A first recombination region is provided at least in a region of a sixth semiconductor layer which is at a second main surface side of a seventh semiconductor layer and which overlaps the seventh semiconductor layer as seen in plan view.Type: ApplicationFiled: July 12, 2021Publication date: March 17, 2022Applicant: Mitsubishi Electric CorporationInventors: Tetsuo TAKAHASHI, Hidenori FUJII, Shigeto HONDA
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Publication number: 20210384189Abstract: A semiconductor device in which a transistor and a diode are formed on a common semiconductor substrate is provided. The semiconductor substrate includes a transistor region in which a transistor is formed and a diode region in which a diode is formed. At least one first electrode on a second main surface side of the transistor region and at least one second electrode on a second main surface side of the diode region are made of different materials.Type: ApplicationFiled: March 10, 2021Publication date: December 9, 2021Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Takahiro NAKATANI, Tetsuya NITTA
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Patent number: 10658523Abstract: The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p+-type anode layer disposed to include a position right under a portion where the wire is connected; and a p?-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p+-type anode layer is higher than an impurity concentration of the p?-type anode layer.Type: GrantFiled: October 17, 2018Date of Patent: May 19, 2020Assignee: Mitsubishi Electric CorporationInventors: Shigeto Honda, Fumihito Masuoka, Yuki Haraguchi
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Publication number: 20190157466Abstract: The semiconductor device according to the present invention includes: an n-type semiconductor substrate; a p-type anode layer provided in a front surface of the n-type semiconductor substrate; an anode electrode provided on the p-type anode layer; and a wire connected to the anode electrode, the p-type anode layer includes: a p+-type anode layer disposed to include a position right under a portion where the wire is connected; and a p?-type anode layer disposed to exclude the position right under the portion where the wire is connected, and an impurity concentration of the p+-type anode layer is higher than an impurity concentration of the p?-type anode layer.Type: ApplicationFiled: October 17, 2018Publication date: May 23, 2019Applicant: Mitsubishi Electric CorporationInventors: Shigeto HONDA, Fumihito MASUOKA, Yuki HARAGUCHI
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Publication number: 20170154955Abstract: A semiconductor device includes: a semiconductor substrate; a device region on the semiconductor substrate; a planar edge termination region on the semiconductor substrate to surround the device region; and a passivation film covering the edge termination region, wherein the passivation film includes a semi-insulating film directly contacting the semiconductor substrate.Type: ApplicationFiled: June 6, 2016Publication date: June 1, 2017Applicant: Mitsubishi Electric CorporationInventors: Tatsuo HARADA, Shigeto HONDA, Akito NISHII, Ze CHEN
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Patent number: 9431479Abstract: In a semiconductor device according to the present invention, an electrode layer and a recessed part are formed on a surface of a semiconductor substrate. Further, in the semiconductor substrate, a RESURF layer that is in contact with a bottom surface of the recessed part and the electrode layer is formed. In addition, an insulating film is formed on an upper surface of the semiconductor substrate so as to fill the recessed part. Moreover, a field plate electrode is formed on the insulating film above the recessed part.Type: GrantFiled: July 28, 2010Date of Patent: August 30, 2016Assignee: Mitsubishi Electric CorporationInventors: Shigeto Honda, Atsushi Narazaki, Kaoru Motonami
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Patent number: 8614448Abstract: A semiconductor device includes a semiconductor substrate having a collector layer in which the carrier concentration is maximized at a carrier concentration peak position that is 1 ?m or more from a surface of the semiconductor substrate. The semiconductor device further includes a collector electrode formed in contact with a surface of the collector layer.Type: GrantFiled: September 20, 2011Date of Patent: December 24, 2013Assignee: Mitsubishi Electric CorporationInventor: Shigeto Honda
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Patent number: 8552428Abstract: A power semiconductor device according to the present invention, which has a termination structure in which a field plate is provided on an insulating film filled in a recessed region formed in a semiconductor substrate and includes a plurality of unit cells connected in parallel, includes: a gate wiring region in which gate wiring electrically connected to each gate electrode of the plurality of unit cells is provided; and a gate pad region electrically connected to the gate wiring region, wherein the gate wiring region is disposed on the insulating film filled in a recessed region formed in the semiconductor substrate.Type: GrantFiled: December 7, 2010Date of Patent: October 8, 2013Assignee: Mitsubishi Electric CorporationInventor: Shigeto Honda
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Patent number: 8450183Abstract: A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.Type: GrantFiled: December 7, 2010Date of Patent: May 28, 2013Assignee: Mitsubishi Electric CorporationInventors: Ryoichi Fujii, Shigeto Honda, Atsushi Narazaki, Kaoru Motonami
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Patent number: 8435417Abstract: A passivation film having a predetermined width from an outer peripheral end portion toward an inner side and extending along the outer peripheral end portion is formed on a front surface of a semiconductor substrate. An outer peripheral end surface orthogonal to the front surface and a rear surface is formed by grinding the outer peripheral end portion of the semiconductor substrate. A thickness of the semiconductor substrate is reduced to a predetermined thickness by grinding the rear surface. The ground rear surface is etched by discharging a mixed acid onto the rear surface while rotating the semiconductor substrate with the rear surface facing upward, to remove a fracture layer. Thereby, chipping or cracking of the semiconductor substrate is suppressed.Type: GrantFiled: June 30, 2010Date of Patent: May 7, 2013Assignee: Mitsubishi Electric CorporationInventors: Kazunari Nakata, Kaoru Motonami, Atsushi Narazaki, Ayumu Onoyama, Shigeto Honda, Ryoichi Fujii, Tomoya Hirata