Patents by Inventor Shigeto Kobayashi

Shigeto Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9484759
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.
    Type: Grant
    Filed: August 1, 2014
    Date of Patent: November 1, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi Wada, Hajime Mizukami, Mitsuaki Hatakeyama, Shigeto Kobayashi
  • Publication number: 20160164327
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.
    Type: Application
    Filed: August 1, 2014
    Publication date: June 9, 2016
    Inventors: Atsushi Wada, Hajime Mizukami, Mitsuaki Hatakeyama, Shigeto Kobayashi
  • Patent number: 9219362
    Abstract: A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.
    Type: Grant
    Filed: January 18, 2011
    Date of Patent: December 22, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shigeto Kobayashi, Kouichi Yamada, Yoshitaka Ueda, Atsushi Wada
  • Patent number: 9077195
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit specifies the kind of charger by detecting the voltages of a DP terminal and a DM terminal. The charger detection circuit detects open, pull-up, pull-down of at least one of the DP terminal and the DM terminal or formation of a short circuit between both the terminals.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 7, 2015
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Atsushi Wada, Hajime Mizukami, Mitsuaki Hatakeyama, Shigeto Kobayashi
  • Patent number: 9057816
    Abstract: The invention provides a resin-coated optical fiber, including at least: a glass optical fiber composed of a core and a clad for coating the core; a primary layer made of UV-curing resin in contact with the glass optical fiber; and a secondary layer made of the UV-curing resin disposed on an outer periphery of the primary layer, wherein the primary layer has a two-layer structure of an inner layer in contact with a surface of the clad, and an outer layer for coating the inner layer, wherein the UV-curing resin of the inner layer has a Young's modulus of 0.9 MPa or more and 3.0 MPa or less at room temperature in a film state based on JIS standard K7113, and the UV-curing resin of the outer layer has a Young's modulus of 0.1 MPa or more and 0.7 MPa or less at room temperature in a film state based on JIS standard K7113.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: June 16, 2015
    Assignee: HITACHI METALS, LTD.
    Inventors: Shinji Hinoshita, Tetsuya Sukegawa, Tomokazu Hiyama, Shigeto Kobayashi, Natsuki Kamiya, Bing Yao
  • Patent number: 8970165
    Abstract: A determination circuit includes a first detecting unit that detects whether first and second power-supply terminals are connected based on a voltage at the second power-supply terminal of a coupling unit that includes the second power-supply terminal connectable to the first power-supply terminal of a device including first and second terminals, and third and fourth terminals connectable respectively to the first and the second terminals. The determination circuit also includes a voltage applying unit that applies first and second voltages to the third and fourth terminals respectively, a second detecting unit that detects that the first and the second terminals are connected to the third and the fourth terminals, respectively, and a discrimination unit that discriminates a type of the device based on voltages at the third and the fourth terminals connected to the first and second terminals, respectively.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: March 3, 2015
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atsushi Wada, Shigeto Kobayashi
  • Publication number: 20140340026
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.
    Type: Application
    Filed: August 1, 2014
    Publication date: November 20, 2014
    Inventors: Atsushi Wada, Hajime Mizukami, Mitsuaki Hatakeyama, Shigeto Kobayashi
  • Patent number: 8796988
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: August 5, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atsushi Wada, Hajime Mizukami, Mitsuaki Hatakeyama, Shigeto Kobayashi
  • Patent number: 8749221
    Abstract: A power supply detecting circuit detects feeding of power to a power supply terminal from the outside. A control unit identifies an accessory device connected to the connector based on a detection result acquired by the identification terminal voltage detecting circuit and a detection result acquired by the power supply detecting circuit. The identification terminal voltage detecting circuit can narrow down accessory device candidates based on whether or not there is feeding of power detected by the power supply detecting circuit.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 10, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atsushi Wada, Shigeto Kobayashi
  • Patent number: 8654493
    Abstract: A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: February 18, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Atsushi Wada, Kouichi Yamada, Shigeto Kobayashi
  • Patent number: 8513716
    Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 20, 2013
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Yoshitaka Ueda, Kouichi Yamada, Atsushi Wada, Shigeto Kobayashi
  • Publication number: 20130154547
    Abstract: A determination circuit includes a first detecting unit that detects whether first and second power-supply terminals are connected based on a voltage at the second power-supply terminal of a coupling unit that includes the second power-supply terminal connectable to the first power-supply terminal of a device including first and second terminals, and third and fourth terminals connectable respectively to the first and the second terminals. The determination circuit also includes a voltage applying unit that applies first and second voltages to the third and fourth terminals respectively, a second detecting unit that detects that the first and the second terminals are connected to the third and the fourth terminals, respectively, and a discrimination unit that discriminates a type of the device based on voltages at the third and the fourth terminals connected to the first and second terminals, respectively.
    Type: Application
    Filed: November 19, 2012
    Publication date: June 20, 2013
    Inventors: Atsushi Wada, Shigeto Kobayashi
  • Publication number: 20120256596
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit specifies the kind of charger by detecting the voltages of a DP terminal and a DM terminal. The charger detection circuit detects open, pull-up, pull-down of at least one of the DP terminal and the DM terminal or formation of a short circuit between both the terminals.
    Type: Application
    Filed: March 26, 2012
    Publication date: October 11, 2012
    Inventors: Atsushi WADA, Hajime MIZUKAMI, Mitsuaki HATAKEYAMA, Shigeto KOBAYASHI
  • Publication number: 20120249119
    Abstract: A power supply detecting circuit detects feeding of power to a power supply terminal from the outside. A control unit identifies an accessory device connected to the connector based on a detection result acquired by the identification terminal voltage detecting circuit and a detection result acquired by the power supply detecting circuit. The identification terminal voltage detecting circuit can narrow down accessory device candidates based on whether or not there is feeding of power detected by the power supply detecting circuit.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Inventors: Atsushi Wada, Shigeto Kobayashi
  • Publication number: 20120250204
    Abstract: A first voltage dividing circuit is connected between a power feeding line to feed power from an external power supply to an internal circuit, and a fixed potential to divide a voltage of the power feeding line. A first comparator compares a divided voltage, which has been divided by the first voltage dividing circuit, with a reference voltage, and outputs a signal to turn off a power switch inserted into the power feeding line when the divided voltage exceeds the reference voltage. A first transistor is connected between a first node where the divided voltage, which has been divided by the first voltage dividing circuit, is generated, and the fixed potential, and is turned on when the voltage of the first node exceeds a set voltage.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 4, 2012
    Inventors: Atsushi WADA, Kouichi Yamada, Shigeto Kobayashi
  • Publication number: 20120242282
    Abstract: A power supply detection circuit detects power feeding to a VBUS terminal from the outside. A charger detection circuit detects the kind of charger by monitoring voltages of a DP terminal and a DM terminal. A control unit adjusts timing and instructs the charger detection circuit to start a charger kind detection process after a notification of detection of power feeding is received from the power supply detection circuit.
    Type: Application
    Filed: March 26, 2012
    Publication date: September 27, 2012
    Inventors: Atsushi WADA, Hajime Mizukami, Mitsuake Hatakeyama, Shigeto Kobayashi
  • Patent number: 8223058
    Abstract: A capacitor array circuit receives a plurality of input signals, generate a single output signal by combining the plurality of input signals, and output the single output signal. A comparator receives the output signal of the capacitor array circuit. A current source, which is disposed between a predetermined fixed voltage source and an output terminal of the switched-capacitor circuit, supplies the current to the output terminal until the output signal of the comparator changes. A plurality of input capacitors in the capacitor array circuit receives a plurality of input signals in parallel with each other. At least one additional regulating capacitor in the capacitor array circuit store the charge to compensate for an offset component caused by the delay in the comparator. The respective output terminals of the plurality of input capacitors and the at least one additional regulating capacitor are combined into one.
    Type: Grant
    Filed: June 29, 2010
    Date of Patent: July 17, 2012
    Assignees: Semiconductor Components Industries, LLC, Sanyo Semiconductor Co., Ltd.
    Inventors: Shigeto Kobayashi, Atsushi Wada, Toru Dan
  • Publication number: 20120163759
    Abstract: There is provided a resin coated optical fiber, comprising at least: a glass optical fiber composed of a core and a clad for coating the core; a primary layer made of UV-curing resin in contact with the glass optical fiber; and a secondary layer made of the UV-curing resin disposed on an outer periphery of the primary layer, wherein the primary layer has a two-layer structure of an inner layer in contact with a surface of the clad, and an outer layer for coating the inner layer, wherein the UV-curing resin of the inner layer has Young's modulus of 0.9 MPa or more and 3.0 MPa or less at room temperature in a film state based on JIS standard K7113, and the UV-curing resin of the outer layer has Young's modulus of 0.1 MPa or more and 0.7 MPa or less at room temperature in a film state based on JIS standard K7113.
    Type: Application
    Filed: September 23, 2011
    Publication date: June 28, 2012
    Applicant: HITACHI CABLE, LTD.
    Inventors: Shinji HINOSHITA, Tetsuya SUKEGAWA, Tomokazu HIYAMA, Shigeto KOBAYASHI, Natsuki KAMIYA, Bing YAO
  • Publication number: 20110186935
    Abstract: A MOS transistor includes a gate electrode formed in a grid pattern, source regions and drain regions each surrounded by the gate electrode, and a source metal wiring connected to the source regions via source contacts and a drain metal wiring connected to the drain regions via drain contacts. The source metal wiring and the drain metal wiring are disposed along one direction of the grid of the gate electrode. Each of the source regions and the drain regions is a rectangular form having its long side along the length direction of each metal wiring. The source metal wiring and the drain metal wiring are each formed in a zigzag manner in the length direction and are respectively connected to the source contacts and the drain contacts.
    Type: Application
    Filed: January 28, 2011
    Publication date: August 4, 2011
    Inventors: Yoshitaka UEDA, Kouichi Yamada, Atsushi Wada, Shigeto Kobayashi
  • Publication number: 20110175449
    Abstract: A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.
    Type: Application
    Filed: January 18, 2011
    Publication date: July 21, 2011
    Inventors: Shigeto KOBAYASHI, Kouichi Yamada, Yoshitaka Ueda, Atsushi Wada