Abstract: A semiconductor integrated circuit device, comprises: an n.sup.+ -type buried layer 12 formed on a surface of a p-type semiconductor substrate 11; an n-type semiconductor layer 71 formed on the n.sup.+ -type buried layer 12; a first p type well 16 formed in the semiconductor layer 71; a second p-type well 18 formed in the semiconductor layer 71 and electrically isolated from the first p-type well 16; an input-protecting N-type MOS transistor 102 formed in the first p-type well 16 and having a drain 22 grounded, a source 25 connected to an input terminal 101 to which an external signal is input, and a gate 23 grounded; and an n.sup.+ -type impurity region 27 grounded and formed in the second p-type well 18. Whenever a negative surge voltage is applied to the input terminal 101, a current path is formed from the ground V.sub.SS to the input terminal 101, by way of the impurity region 27 formed in the second p-type well 18, the n.sup.

Abstract: A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lines, bit line loading means connected to another pair of bit lines and bit line equalizing means provided for the bit lines for equalizing the potential of the bit lines by allowing conduction between the bit lines before data is read from a selected memory cell.

Abstract: A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit generates a second supply voltage (constant voltage) on the basis of the first supply voltage, and supplies the constant voltage to this delay circuit, so that a stable constant delay time can be obtained by the delay circuit without being subjected to the influence of fluctuations of the first supply voltage. All the circuit elements are formed on the same semiconductor substrate. Further, it is preferable to construct the constant voltage supply circuit in such a way that the output voltage thereof is programmable.

Abstract: A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circuit for reading latch data based on second address inputs A0 and A1 corresponding to the plurality of latch circuits, and a control circuit for controlling the sense amplifier to be activated when only the first address input or both first and second address inputs are changed, and to be inactivated when only the second address input is changed.

Abstract: In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to a high level, a pulse generator generates a pulse signal in "1" level and with a given pulse width. In response to this pulse signal, a first MOS transistor is turned on to short paired bit lines. This pulse signal turns on second and third MOS transistors. Then, the potentials on the paired bit lines are pulled up to a power source potential. As a result, of the two bit lines, the bit line which has been set at a low potential immediately after data is written, is charged. A pulse extension/inverting circuit extends the pulse width of the pulse signal generated by a pulse generator by a given time period, and inverts a logical state of the pulse signal.

Abstract: A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripheral circuit for driving the memory cell array is formed in at least one second well region of the opposite conductivity type formed separately from the first well region in the surface area of the semiconductor body. The second well region is set at a bias level deeper than the first well region.