Patents by Inventor Shigetoshi Hosaka

Shigetoshi Hosaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070107845
    Abstract: A semiconductor processing system includes an intermediate structure disposed between an atmospheric pressure entrance transfer chamber and a vacuum common transfer chamber. The intermediate structure includes a transfer passage for a target substrate to pass therein. The transfer passage includes a first buffer chamber a middle transfer chamber and a second buffer chamber detachably connected. An additional processing apparatus is detachably connected to the middle transfer chamber. The intermediate structure is selectively arranged in first or second state. In the first state, the additional processing apparatus performs a vacuum process, while the first buffer chamber is a load-lock chamber. In the second state, the additional processing apparatus performs an atmospheric pressure process, while the second buffer chamber is a load-lock chamber.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 17, 2007
    Inventors: Shigeru Ishizawa, Hiroaki Saeki, Yoshimitsu Tamura, Shigetoshi Hosaka, Masahide Itoh, Kazushi Tahara, Yasushi Kodashima
  • Publication number: 20070091135
    Abstract: An image processing method for processing image data to be output by an image forming apparatus is disclosed. The image forming apparatus is configured to form a tone pattern on a recording medium by forming an arrangement of dots on the recording medium. The arrangement of dots is formed on the recording medium by jetting a recording liquid from a recording head while moving the recording head in a main scanning direction a plurality of times and intermittently conveying the recording medium in a sub-scanning direction that perpendicularly intersects the main scanning direction. The method includes the step of generating a mask pattern for moving the recording head in the main scanning direction and forming the dots in an inconsecutive order on the recording medium.
    Type: Application
    Filed: October 23, 2006
    Publication date: April 26, 2007
    Inventors: Shigetoshi Hosaka, Masakazu Yoshida, Takashi Kimura, Masanori Hirano
  • Publication number: 20070085869
    Abstract: An image processing method performs processing to generate image data based on input data and output the image data to an image forming device. The image forming device includes a printing head in which first nozzles for ejecting color ink drops are arranged in a symmetrical formation to forward and backward scanning directions and second nozzles for ejecting black or gray ink drops are arranged in an unsymmetrical formation with respect to the first nozzles. The image forming device is adapted to perform a uni-directional printing or a bidirectional printing with the printing head. In the image processing method, a black generation processing to the input data is performed, and when performing the black generation processing, a black-generation start level for the bidirectional printing is delayed to a shadow-side gradation level from a black-generation start level for the uni-directional printing.
    Type: Application
    Filed: October 16, 2006
    Publication date: April 19, 2007
    Inventors: Masanori Hirano, Masakazu Yoshida, Shigetoshi Hosaka
  • Publication number: 20040238122
    Abstract: A semiconductor processing system includes an intermediate structure (37A, 37B) disposed between an atmospheric pressure entrance transfer chamber (32) and a vacuum common transfer chamber (36). The intermediate structure includes a transfer passage (38A, 38B) for a target substrate (W) to pass therein. The transfer passage includes a first buffer chamber (70), a middle transfer chamber (72), and a second buffer chamber (74) detachably connected. An additional processing apparatus (110, 110A) is detachably connected to the middle transfer chamber. The intermediate structure is selectively arranged in first or second state. In the first state, the additional processing apparatus (110) performs a vacuum process, while the first buffer chamber (70) is a load-lock chamber. In the second state, the additional processing apparatus (110A) performs an atmospheric pressure process, while the second buffer chamber (74) is a load-lock chamber.
    Type: Application
    Filed: February 12, 2004
    Publication date: December 2, 2004
    Inventors: Shigeru Ishizawa, Hiroaki Saeki, Yoshimitsu Tamura, Shigetoshi Hosaka, Masahide Itoh, Kazushi Tahara, Yasushi Kodashima
  • Publication number: 20030094135
    Abstract: The present invention provides a gas process apparatus that realizes uniform exhaust without depending on process conditions, a gas process chamber that constitutes the gas process apparatus, a baffle plate mounted on the gas process chamber, a method of producing the baffle plate, and an apparatus for producing the baffle plate. The baffle plate of the present invention serves as a partition between a process space in which a chemical process is carried out with a supplied gas, and a duct that is adjacent to the process space and functions to discharge exhaust gas generated as a result of the chemical process. In accordance with the difference between the pressures on both sides of the baffle plate, which difference varies depending on the location on the baffle plate, the baffle holes are disposed on a plurality of locations on the baffle plate.
    Type: Application
    Filed: October 11, 2002
    Publication date: May 22, 2003
    Inventors: Taro Komiya, Hatsuo Osada, Shigetoshi Hosaka, Tomihiro Yonenaga, Masayuki Tomoyasu
  • Patent number: 6066558
    Abstract: The multilevel interconnection forming method of the present invention comprises the following. A metal film containing aluminum is deposited on an insulating film of a substrate, and the metal film is patterned, to form a wiring layer of a first layer. An interlayer dielectric film forming part of the first layer is formed on an entire surface of the substrate, such that the interlayer dielectric film covers the wiring layer from upside. A hole is formed at a predetermined position of the interlayer dielectric film such that the hole reaches the wiring layer of the first layer. Aluminum is selectively deposited and filled into the hole by a CVD method, such that the aluminum is filled at a volume ratio smaller than 100% with respect to the hole. An active metal film is formed on an entire upper surface of an interlayer dielectric film including the hole filled with the aluminum. A metal layer containing aluminum is formed on the active metal film.
    Type: Grant
    Filed: March 4, 1997
    Date of Patent: May 23, 2000
    Assignee: Tokyo Electron Limited
    Inventors: Yumiko Kawano, Shigetoshi Hosaka, Yuichi Wada, Hiroshi Kobayashi, Tetsuya Yano