Patents by Inventor Shigetoshi Sota
Shigetoshi Sota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11069783Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: GrantFiled: October 20, 2020Date of Patent: July 20, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
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Patent number: 11056589Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: GrantFiled: October 14, 2020Date of Patent: July 6, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
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Patent number: 11056563Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: GrantFiled: October 20, 2020Date of Patent: July 6, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
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Publication number: 20210050444Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: ApplicationFiled: October 14, 2020Publication date: February 18, 2021Inventors: Yoshihiro MATSUSHIMA, Shigetoshi SOTA, Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Ryou KATO
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Publication number: 20210036114Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Takeshi IMAMURA, Mitsuaki SAKAMOTO, Kazuma YOSHIDA, Masaaki HIRAKO, Yasuyuki MASUMOTO, Shigetoshi SOTA, Tomonari OOTA
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Publication number: 20210036113Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: ApplicationFiled: October 20, 2020Publication date: February 4, 2021Inventors: Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Takeshi IMAMURA, Mitsuaki SAKAMOTO, Kazuma YOSHIDA, Masaaki HIRAKO, Yasuyuki MASUMOTO, Shigetoshi SOTA, Tomonari OOTA
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Patent number: 10854744Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: GrantFiled: June 20, 2019Date of Patent: December 1, 2020Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Yoshihiro Matsushima, Shigetoshi Sota, Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Ryou Kato
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Patent number: 10636906Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.Type: GrantFiled: December 26, 2017Date of Patent: April 28, 2020Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Tomonari Ota, Shigetoshi Sota, Eiji Yasuda, Takeshi Imamura, Toshikazu Imai, Ryosuke Okawa, Kazuma Yoshida, Masaaki Hirako, Dohwan Ahn
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Publication number: 20190319126Abstract: A semiconductor device includes an N-type semiconductor substrate comprising silicon, an N-type low-concentration impurity layer that is in contact with the upper surface of the N-type semiconductor substrate, a metal layer that is in contact with the entire lower surface of the N-type semiconductor substrate and has a thickness of at least 20 ?m, and first and second vertical MOS transistors formed in the low-concentration impurity layer. The ratio of the thickness of the metal layer to the thickness of a semiconductor layer containing the N-type semiconductor substrate and the low-concentration impurity layer is greater than 0.27. The semiconductor device further includes a support comprising a ceramic material and bonded to the entire lower surface of the metal layer only via a bonding layer.Type: ApplicationFiled: June 20, 2019Publication date: October 17, 2019Inventors: Yoshihiro MATSUSHIMA, Shigetoshi SOTA, Eiji YASUDA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Ryou KATO
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Publication number: 20190157403Abstract: A semiconductor device includes a semiconductor substrate including a first conductivity-type impurity, a low-concentration impurity layer including a first conductivity-type impurity having a concentration lower than a concentration of the first conductivity-type impurity in the semiconductor substrate, a backside electrode including a metal material, and first and second transistors in the low-concentration impurity layer. The first transistor includes a first source electrode and a first gate electrode on a surface of the low-concentration impurity layer, the second transistor includes a second source electrode and a second gate electrode on the surface of the low-concentration impurity layer. The semiconductor substrate serves as a common drain region of the transistors.Type: ApplicationFiled: January 29, 2019Publication date: May 23, 2019Inventors: Eiji Yasuda, Toshikazu Imai, Ryosuke Okawa, Takeshi Imamura, Mitsuaki Sakamoto, Kazuma Yoshida, Masaaki Hirako, Yasuyuki Masumoto, Shigetoshi Sota, Tomonari Oota
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Publication number: 20180122939Abstract: A semiconductor device in chip size package includes first and second metal oxide semiconductor transistors both vertical transistors formed in first and second regions obtained by dividing the semiconductor device into halves. The first metal oxide semiconductor transistor includes one or more first gate electrodes and four or more first source electrodes provided in one major surface, each of the first gate electrodes is surrounded, in top view, by the first source electrodes, and for any combination of a first gate electrode and a first source electrode, closest points between the first gate and first source electrodes are on a line inclined to a chip side. The second metal oxide semiconductor transistor includes the same structure as the first metal oxide semiconductor transistor. A conductor that connects the drains of the first and second metal oxide semiconductor transistors is provided in the other major surface of the semiconductor device.Type: ApplicationFiled: December 26, 2017Publication date: May 3, 2018Inventors: Tomonari OTA, Shigetoshi SOTA, Eiji YASUDA, Takeshi IMAMURA, Toshikazu IMAI, Ryosuke OKAWA, Kazuma YOSHIDA, Masaaki HIRAKO, Dohwan AHN
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Patent number: D813182Type: GrantFiled: January 26, 2017Date of Patent: March 20, 2018Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Toshikazu Imai, Ryosuke Okawa, Eiji Yasuda, Takeshi Imamura, Kazuma Yoshida, Shigetoshi Sota