Patents by Inventor Shigetoshi Takayanagi

Shigetoshi Takayanagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4261792
    Abstract: A metallization or conductor or semiconductor layer formed over one major surface of a semiconductor wafer subjected to anodizing to form an anodized coating which has excellent adherence to the conductor or semiconductor layer and which is used as an etching mask when the conductor or semiconductor layer is etched.
    Type: Grant
    Filed: August 9, 1978
    Date of Patent: April 14, 1981
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Tsuji, Takashi Ohzone, Shigetoshi Takayanagi
  • Patent number: 4256513
    Abstract: A photoelectric conversion device such as a solar cell in which electrodes formed from a conductive paste make ohmic contact with the surfaces of impurity diffused layers respectively formed in a semiconductor substrate. The conductive paste contains ultrafine particles of silver and gold as its principal solid components. The conductive paste further contains, as its additional principal solid components, ultrafine particles of a metal having a eutectic temperature lower than that of silver when alloyed with the semiconductor and a powdery glass material not containing any lead oxide glass component. The electrodes provided by the conductive paste exhibit excellent electrical properties when the conductive paste is subjected to firing treatment at a temperature of about 600.degree. C. Thus, when, for example, the semiconductor substrate is of n-type silicon and a p.sup.+ -type diffused layer is formed in one of its major surfaces to form a p.sup.
    Type: Grant
    Filed: October 16, 1979
    Date of Patent: March 17, 1981
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Manabu Yoshida, Jun Fukuchi, Shigetoshi Takayanagi
  • Patent number: 4185291
    Abstract: A junction-type FET comprising a semiconductor substrate 21 of a first conductivity type, and island region 22 of a second conductivity type which comprises a channel region and is selectively formed in the semiconductor substrate 21, and a buried isolating region 27 which is selected from the group consisting of an intrinsic layer, a low impurity concentration layer of the second conductivity type and a layer of first conductivity type, the buried isolating layer being formed by ion implantation of impurities of the first conductivity type in the island region 22 while keeping the impurity concentration at the surface thereof relatively high, and the buried isolating layer substantially isolating the channel region from the surface.
    Type: Grant
    Filed: June 16, 1978
    Date of Patent: January 22, 1980
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takashi Hirao, Shigetoshi Takayanagi, Takeshi Onuma, Toshio Sugawa, Kaoru Inoue