Patents by Inventor Shigetoshi Yamada

Shigetoshi Yamada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6954249
    Abstract: In a liquid crystal display device for displaying a visible image by controlling the alignment of a liquid crystal disposed between a pair of transparent substrates (1a, 1b), a resistance element (8, 13, 18, 28, 40) for changing a voltage which will be imposed in the liquid crystal is directly formed on the transparent substrate (1a) by ITO or the like. One or ones of the resistance branches (8a) of a resistance pattern (8) are cut off by a laser beam to thereby change the resistance value of the resistance pattern (8) so that a voltage which will be imposed on the liquid crystal is adjusted. A peripheral circuit including a capacitor and/or the like may be directly formed on the transparent substrate (1a) in addition to the resistance pattern (8). The peripheral circuit may be formed to a portion located between the pair of transparent substrates (1a, 1b).
    Type: Grant
    Filed: April 21, 1998
    Date of Patent: October 11, 2005
    Assignee: Seiko Epson Corporation
    Inventors: Eiji Muramatsu, Shigetoshi Yamada, Minoru Ikegami
  • Publication number: 20020060767
    Abstract: In a liquid crystal display device for displaying a visible image by controlling the alignment of a liquid crystal disposed between a pair of transparent substrates (1a, 1b), a resistance element (8, 13, 18, 28, 40) for changing a voltage which will be imposed in the liquid crystal is directly formed on the transparent substrate (1a) by ITO or the like. One or ones of the resistance branches (8a) of a resistance pattern (8) are cut off by a laser beam to thereby change the resistance value of the resistance pattern (8) so that a voltage which will be imposed on the liquid crystal is adjusted. A peripheral circuit including a capacitor and/or the like may be directly formed on the transparent substrate (1a) in addition to the resistance pattern (8). The peripheral circuit may be formed to a portion located between the pair of transparent substrates (1a, 1b).
    Type: Application
    Filed: March 8, 1999
    Publication date: May 23, 2002
    Inventors: EIJI MURAMATSU, SHIGETOSHI YAMADA, MINORU IKEGAMI
  • Patent number: 6211935
    Abstract: An alignment mark 4K is formed by a through hole in an opaque circuit substrate 1. An alignment mark 4I of an IC chip 3 is photographed by a CCD camera 9 through the alignment mark hole 4K, and the position of the IC chip 3 is adjusted so that the IC side alignment mark 4I is in the prescribed positional relationship to the substrate side alignment mark hole 4K. Then, the IC chip 3 is adhered to the circuit substrate 1 using the adhesive such as ACF 2, etc. Both alignment marks 4I and 4K can be simultaneously photographed by one photograph of the camera 9, and the alignment can be continuously performed.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: April 3, 2001
    Assignee: Seiko Epson Corporation
    Inventor: Shigetoshi Yamada
  • Patent number: 6128063
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: October 3, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5986342
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: June 27, 1997
    Date of Patent: November 16, 1999
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda
  • Patent number: 5737272
    Abstract: A liquid crystal display apparatus is provided which requires a small, thin and compact area for mounting semiconductor chips for driving liquid crystal and, accordingly, has a reduced cost. Semiconductor chips for driving liquid crystal are mounted on a surface (for example, a first layer) of a multi-layer substrate. The surface has input lines to the chips and output lines from the chips. The input lines have lands for connecting adjacent multi-layer substrates to each other. At least one intermediate layer is formed between an upper layer and a lower layer, the intermediate layer having bus lines. The bus lines and the input lines of the first layer are connected to one another via through holes in the first layer. The output lines of the first layer and terminals of the third layer are connected to one another via through holes in the first, second and third layers.
    Type: Grant
    Filed: September 8, 1993
    Date of Patent: April 7, 1998
    Assignee: Seiko Epson Corporation
    Inventors: Kenji Uchiyama, Eiji Muramatsu, Masaru Kamimura, Shigetoshi Yamada, Kenichi Maruyama, Seiichi Sakura, Kazuaki Furuichi, Kinichi Maeda