Patents by Inventor Shigeya Kimura

Shigeya Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140252395
    Abstract: According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taisuke SATO, Shigeya Kimura, Kotaro Zaima, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20140252311
    Abstract: According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer of an n-type, a second semiconductor layer of a p-type, and a light emitting unit. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer includes a nitride semiconductor. The light emitting unit is provided between the first semiconductor layer and the second semiconductor layer. The light emitting unit includes a plurality of well layers stacked alternately with a plurality of barrier layers. The well layers include a first p-side well layer most proximal to the second semiconductor layer, and a second p-side well layer second most proximal to the second semiconductor layer. A localization energy of excitons of the first p-side well layer is smaller than a localization energy of excitons of the second p-side well layer.
    Type: Application
    Filed: February 14, 2014
    Publication date: September 11, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeya KIMURA, Hajime Nago, Shinya Nunoue
  • Patent number: 8816367
    Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first and second semiconductor layers and a light emitting layer. The first electrode includes a first region, a second region, and a third region provided between them. The first semiconductor layer includes a first portion on the first region and a second portion on the second region. The light emitting layer includes a third portion on the first portion and a fourth portion on the second portion. The second semiconductor layer includes a fifth portion on the third portion and a sixth portion on the fourth portion. The insulating layer is provided between the first and second portions on the third region and between the third and fourth portions. The second electrode includes a seventh portion provided on the insulating layer, eighth and ninth portions contacting side surfaces of the fifth and sixth portions.
    Type: Grant
    Filed: December 26, 2012
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Kotaro Zaima, Hiroshi Ono, Shinji Yamada, Shigeya Kimura, Naoharu Sugiyama, Shinya Nunoue
  • Publication number: 20140183447
    Abstract: According to one embodiment, a semiconductor light emitting element includes an n-type semiconductor layer including a nitride semiconductor, a p-type semiconductor layer and a light emitting layer. The p-type semiconductor layer includes a first p-side layer of Alx1Ga1?x1N (0?x1<1) including Mg, a second p-side layer of Alx2Ga1?x2N (0<x2<1) including Mg and a third p-side layer of Alx3Ga1?x3N (x2<x3<1) including Mg. The light emitting layer is provided between the n-type semiconductor layer and the second p-side layer. The light emitting layer includes barrier layers and well layers. Each of the well layers is provided between the barrier layers. A p-side barrier layer of the barrier layers most proximal to the second p-side layer includes a first layer of Alz1Ga1?z1N (0?z1), and a second layer of Alz2Ga1?z2N (z1<z2<x2).
    Type: Application
    Filed: December 12, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime NAGO, Shigeya KIMURA, Yoshiyuki HARADA, Shinya NUNOUE
  • Publication number: 20140183446
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting layer. The p-type semiconductor layer includes a first p-side layer, a second p-side layer, and a third p-side layer. A concentration profile of Mg of a p-side region includes a first portion, a second portion, a third portion, a fourth portion, a fifth portion, a sixth portion and a seventh portion. The p-side region includes the light emitting layer, the second p-side layer, and the third p-side layer. A Mg concentration of the sixth portion is not less than 1×1020 cm?3 and not more than 3×1020 cm?3. The Al concentration is 1/100 of the maximum value at a second position. A Mg concentration at the second position is not less than 2×1018 cm?3.
    Type: Application
    Filed: December 2, 2013
    Publication date: July 3, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime NAGO, Yoshiyuki HARADA, Shigeya KIMURA, Hisashi YOSHIDA, Shinya NUNOUE
  • Patent number: 8766311
    Abstract: According to one embodiment, a semiconductor light emitting device includes a p-type semiconductor layer, an n-type semiconductor layer, a light emitting layer, a p-side electrode and an n-side electrode. The p-type semiconductor layer includes a nitride semiconductor and has a first major surface. The n-type semiconductor layer includes a nitride semiconductor and has a second major surface. The light emitting layer is provided between the n-type semiconductor layer and the p-type semiconductor layer. The p-side electrode contacts a part of the p-type semiconductor layer on the first major surface. The n-side electrode contacts a part of the n-type semiconductor layer on the second major surface. The n-side electrode is provided outside and around the p-side electrode in a plan view along a direction from the p-type semiconductor layer to the n-type semiconductor layer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: July 1, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taisuke Sato, Shigeya Kimura, Kotaro Zaima, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20140153602
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8729578
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The second semiconductor layer is provided on a [0001]-direction side of the first semiconductor layer. The light emitting layer includes a first well layer, a second well layer and a first barrier layer. An In composition ratio of the barrier layer is lower than that of the first well layer and the second well layer. The barrier layer includes a first portion and a second portion. The second portion has a first region and a second region. The first region has a first In composition ratio higher than that of the first portion. The second region is provided between the first region and the first well layer. The second region has a second In composition ratio lower than the first In composition ratio.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 20, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Hajime Nago, Koichi Tachibana, Shinya Nunoue
  • Publication number: 20140124735
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).
    Type: Application
    Filed: January 14, 2014
    Publication date: May 8, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi TACHIBANA, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Publication number: 20140110667
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting portion, a first layer, a second layer, and an intermediate layer. The semiconductor layers include nitride semiconductor. The light emitting portion is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a quantum well layer. The first layer is provided between the light emitting portion and the p-type semiconductor layer and includes AlX1Ga1-x1N having first Al composition ratio x1. The second layer is provided between the first layer and the p-type semiconductor layer and includes Alx2Ga1-x2N having second Al composition ratio x2 higher than the first Al composition ratio x1. The intermediate layer is provided between the first layer and the light emitting portion and has a thickness not smaller than 3 nanometers and not larger than 8 nanometers and includes Inz1Ga1-z1N (0?z1<1).
    Type: Application
    Filed: December 30, 2013
    Publication date: April 24, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Koichi TACHIBANA, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8704268
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer and a light emitting layer. The emitting layer is provided between the n-type layer and the p-type layer, and includes a plurality of barrier layers and a plurality of well layers, being alternately stacked. The p-side barrier layer being closest to the p-type layer among the plurality of barrier layer includes a first layer and a second layer, containing group III elements. An In composition ratio in the group III elements of the second layer is higher than an In composition ratio in the group III elements of the first layer. An average In composition ratio of the p-side layer is higher than an average In composition ratio of an n-side barrier layer that is closest to the n-type layer among the plurality of barrier layers.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: April 22, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Koichi Tachibana, Shinya Nunoue
  • Patent number: 8698192
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8674338
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Patent number: 8653498
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked structural body, a first electrode; and a second electrode. The stacked structural body includes a first semiconductor layer of n-type, a second semiconductor layer of p-type, and a light emitting portion provided therebetween. The first electrode includes a first contact electrode portion. The second electrode includes a second contact electrode portion and a p-side pad electrode. A sheet resistance of the second contact electrode portion is lower than a sheet resistance of the first semiconductor layer. The p-side pad electrode is provided farther inward than a circumscribed rectangle of the first contact electrode portion, and the first contact electrode portion is provided farther outward than a circumscribed rectangle of the p-side pad electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Taisuke Sato, Toshihide Ito, Takahiro Sato, Toshiyuki Oka, Shinya Nunoue
  • Publication number: 20140045289
    Abstract: According to one embodiment, a method is disclosed for manufacturing a nitride semiconductor layer. The method can include forming a first nitride semiconductor layer on a substrate in a reactor supplied with a first carrier gas and a first source gas. The first nitride semiconductor layer includes indium. The first carrier gas includes hydrogen supplied into the reactor at a first flow rate and includes nitrogen supplied into the reactor at a second flow rate. The first source gas includes indium and nitrogen and supplied into the reactor at a third flow rate. The first flow rate is not less than 0.07% and not more than 0.15% of a sum of the first flow rate, the second flow rate, and the third flow rate.
    Type: Application
    Filed: March 13, 2013
    Publication date: February 13, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hajime NAGO, Yoshiyuki Harada, Hisashi Yoshida, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8648381
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting portion, a first layer, a second layer, and an intermediate layer. The semiconductor layers include nitride semiconductor. The light emitting portion is provided between the n-type semiconductor layer and the p-type semiconductor layer and includes a quantum well layer. The first layer is provided between the light emitting portion and the p-type semiconductor layer and includes Alx1Ga1-x1N having first Al composition ratio x1. The second layer is provided between the first layer and the p-type semiconductor layer and includes Alx2Ga1-x2N having second Al composition ratio x2 higher than the first Al composition ratio x1. The intermediate layer is provided between the first layer and the light emitting portion and has a thickness not smaller than 3 nanometers and not larger than 8 nanometers and includes Inz1Ga1-z1N (0?z1<1).
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: February 11, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Publication number: 20140034978
    Abstract: According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a second semiconductor layer and a light emitting layer. The second semiconductor layer is provided on a [0001]-direction side of the first semiconductor layer. The light emitting layer includes a first well layer, a second well layer and a first barrier layer. An In composition ratio of the barrier layer is lower than that of the first well layer and the second well layer. The barrier layer includes a first portion and a second portion. The second portion has a first region and a second region. The first region has a first In composition ratio higher than that of the first portion. The second region is provided between the first region and the first well layer. The second region has a second In composition ratio lower than the first In composition ratio.
    Type: Application
    Filed: March 14, 2013
    Publication date: February 6, 2014
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Shigeya KIMURA, Hajime NAGO, Koichi TACHIBANA, Shinya NUNOUE
  • Patent number: 8643044
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked structure body, first and second electrodes, and a pad layer. The body includes first semiconductor layer of a first conductivity type, a light emitting layer, and a second semiconductor layer of second conductivity type. The first semiconductor layer has first and second portions. The light emitting layer is provided on the second portion. The second semiconductor layer is provided on the light emitting layer. The first electrode is provided on the first portion. The second electrode is provided on the second semiconductor layer and is transmittable to light emitted from the light emitting layer. The pad layer is connected to the second electrode. A transmittance of the pad layer is lower than that of the second electrode. A sheet resistance of the second electrode increases continuously along a direction from the pad layer toward the first electrode.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: February 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Shigeya Kimura, Toshiki Hikosaka, Taisuke Sato, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8623683
    Abstract: According to one embodiment, in a nitride semiconductor light emitting device, a first clad layer includes an n-type nitride semiconductor. An active layer is formed on the first clad layer, and includes an In-containing nitride semiconductor. A GaN layer is formed on the active layer. A first AlGaN layer is formed on the GaN layer, and has a first Al composition ratio. A p-type second AlGaN layer is formed on the first AlGaN layer, has a second Al composition ratio higher than the first Al composition ratio, and contains a larger amount of Mg than the GaN layer and the first AlGaN layer. A second clad layer is formed on the second AlGaN layer, and includes a p-type nitride semiconductor.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: January 7, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Nago, Koichi Tachibana, Toshiyuki Oka, Shigeya Kimura, Shinya Nunoue
  • Publication number: 20130328055
    Abstract: According to one embodiment, a semiconductor light emitting device includes first and second electrodes, first, second and third semiconductor layers, and a light emitting layer. The first semiconductor layer of a first conductivity type is provided on the first electrode. The light emitting layer is provided on the first semiconductor layer. The second semiconductor layer of a second conductivity type is provided on the light emitting layer. The third semiconductor layer with low impurity concentration is provided on a part of the second semiconductor layer. The second electrode includes a pad section and a narrow wire section. The pad section is provided on the third semiconductor layer. The narrow wire section extends out from the pad section and includes an extending portion extending along a plane perpendicular to a stacking direction. The narrow wire section is in contact with the second semiconductor layer.
    Type: Application
    Filed: December 21, 2012
    Publication date: December 12, 2013
    Inventors: Jumpei TAJIMA, Kotaro Zaima, Shigeya Kimura, Hiroshi Ono, Shinji Yamada, Satoshi Mitsugi, Naoharu Sugiyama, Shinya Nunoue