Patents by Inventor Shigeyasu Mori

Shigeyasu Mori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11881187
    Abstract: A polymer dispersion type liquid crystal device includes a pair of transparent substrates; a pair of transparent electrodes provided between the pair of transparent substrates; a liquid crystal layer formed by filling a polymer dispersion type liquid crystal between the pair of transparent electrodes; and a driving circuit that applies a voltage between the pair of transparent electrodes to set the liquid crystal layer to a non-scattering state or a scattering state. The driving circuit applies a direct current voltage that periodically inverts a polarity between the pair of transparent electrodes.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: January 23, 2024
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shigeyasu Mori, Yoshihiro Onishi
  • Patent number: 11510623
    Abstract: A patchable biosensor includes a substrate extending in a longitudinal direction and being stretchable for being patched to a surface of a living body and an electronic component disposed on a one-side surface in a thickness direction of the substrate and extending in the longitudinal direction. The longitudinal direction of the electronic component crosses the longitudinal direction of the substrate.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: November 29, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shigeyasu Mori, Ryoma Yoshioka, Eiji Toyoda, Keiji Takemura
  • Publication number: 20220223030
    Abstract: A data acquisition method and a signal measurement system that allow measured data to be easily and reliably obtained from memory are provided. The signal measurement system includes a reception device on which a plurality of devices storing measurement data are placed, a probe mechanism configured to be able to come into contact with the plurality of devices placed on the reception device, a control circuit configured to read, in parallel, the measurement data from the plurality of devices with the probe mechanism, and an information processing apparatus configured to process, in parallel, the measurement data having been read, wherein at a point in time when a subsequent device set is placed on the reception device, the control circuit drives the probe mechanism, and at a point in time when data processing with the information processing apparatus is completed, the control circuit starts reading, in parallel, data from the subsequent device set.
    Type: Application
    Filed: October 11, 2019
    Publication date: July 14, 2022
    Inventors: Ryoma YOSHIOKA, Shigeyasu MORI
  • Publication number: 20220005429
    Abstract: A polymer dispersion type liquid crystal device includes a pair of transparent substrates; a pair of transparent electrodes provided between the pair of transparent substrates; a liquid crystal layer formed by filling a polymer dispersion type liquid crystal between the pair of transparent electrodes; and a driving circuit that applies a voltage between the pair of transparent electrodes to set the liquid crystal layer to a non-scattering state or a scattering state. The driving circuit applies a direct current voltage that periodically inverts a polarity between the pair of transparent electrodes.
    Type: Application
    Filed: March 4, 2020
    Publication date: January 6, 2022
    Inventors: Shigeyasu MORI, Yoshihiro ONISHI
  • Patent number: 11187887
    Abstract: In an electrode substrate (10), a contact hole (19) provided in a first planarizing resin layer (13) is filled with a second planarizing resin layer (16). A TFT (20) is electrically connected to an electrode (14) via the contact hole (19). On the electrode (14), a water repellent layer (18) is provided via a dielectric layer (15) including the second planarizing resin layer (16) and an ion barrier layer (17).
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: November 30, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Tomoko Teranishi, Hao Li, Shigeyasu Mori
  • Publication number: 20210208386
    Abstract: In an electrode substrate (10), a contact hole (19) provided in a first planarizing resin layer (13) is filled with a second planarizing resin layer (16). A TFT (20) is electrically connected to an electrode (14) via the contact hole (19). On the electrode (14), a water repellent layer (18) is provided via a dielectric layer (15) including the second planarizing resin layer (16) and an ion barrier layer (17).
    Type: Application
    Filed: January 11, 2017
    Publication date: July 8, 2021
    Applicant: SHARP KABUSHIKI KAISHA
    Inventors: TOMOKO TERANISHI, HAO LI, SHIGEYASU MORI
  • Publication number: 20200289058
    Abstract: A patchable biosensor includes a substrate extending in a longitudinal direction and being stretchable for being patched to a surface of a living body and an electronic component disposed on a one-side surface in a thickness direction of the substrate and extending in the longitudinal direction. The longitudinal direction of the electronic component crosses the longitudinal direction of the substrate.
    Type: Application
    Filed: October 25, 2018
    Publication date: September 17, 2020
    Inventors: Shigeyasu MORI, Ryoma YOSHIOKA, Eiji TOYODA, Keiji TAKEMURA
  • Patent number: 10777887
    Abstract: A scanning antenna includes a TFT substrate including a first dielectric substrate, a plurality of TFTs, a plurality of gate bus lines, a plurality of source bus lines, and a plurality of patch electrodes, a slot substrate including a second dielectric substrate and a slot electrode (55) formed on the first main surface of the second dielectric substrate, a liquid crystal layer provided between the TFT substrate and the slot substrate, and a reflective conductive plate provided opposing a second main surface opposite to the first main surface of the second dielectric substrate via a dielectric layer, and the slot electrode includes a plurality of slots arranged in accordance with the plurality of patch electrodes, and a groove configured to divide the slot electrode into two or more sections, and the TFT substrate includes an opposing metal part arranged opposing the groove, and when viewed from a normal line direction of the first dielectric substrate, the groove is covered with the opposing metal part in th
    Type: Grant
    Filed: October 7, 2016
    Date of Patent: September 15, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takatoshi Orui, Kiyoshi Minoura, Shigeyasu Mori, Makoto Nakazawa, Fumiki Nakano
  • Patent number: 10756409
    Abstract: A scanning antenna including: a TFT substrate including a first dielectric substrate, a TFT, a gate bus line, a source bus line, and a patch electrode; a slot substrate including a second dielectric substrate and a slot electrode formed on a first main surface of the second dielectric substrate; a liquid crystal layer provided between the TFT substrate and the slot substrate; and a reflective conductive plate. The scanning antenna has a tiling structure in which a plurality of scanning antenna portions are bonded together, and each of the plurality of scanning antenna portions includes a TFT substrate portion and a slot substrate portion.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: August 25, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kiyoshi Minoura, Shigeyasu Mori, Makoto Nakazawa, Fumiki Nakano, Takatoshi Orui
  • Patent number: 10720701
    Abstract: A scanning antenna is a scanning antenna in which antenna units U are arranged, and includes a TFT substrate including a first dielectric substrate, TFTs, a plurality of gate bus lines, source bus lines, and patch electrodes; a slot substrate including a second dielectric substrate, and a slot electrode formed on a first main surface of the second dielectric substrate; a liquid crystal layer LC provided between the TFT substrate and the slot substrate; and a reflective conductive plate provided opposing a second main surface of the second dielectric substrate opposite to the first main surface via a dielectric layer. The slot electrode includes slots arranged in correspondence with the plurality of patch electrodes, and each of the patch electrodes is connected to a drain of a corresponding TFT and is supplied with a data signal from a corresponding source bus line while selected by a scanning signal supplied from the gate bus line of the corresponding TFT.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: July 21, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Fumiki Nakano, Kiyoshi Minoura, Shigeyasu Mori, Makoto Nakazawa, Takatoshi Orui
  • Publication number: 20200187859
    Abstract: A biosensor includes a pressure-sensitive adhesive layer for attaching to a surface of a living body, a substrate layer disposed on an upper face of the pressure-sensitive adhesive layer and having a stretching property, a probe disposed on the lower face of the pressure-sensitive adhesive layer, and an electronic component mounted on the substrate layer so as to be connected to the probe, wherein a total thickness of the pressure-sensitive adhesive layer and the substrate layer is 1 ?m or more and less than 100 ?m.
    Type: Application
    Filed: March 15, 2018
    Publication date: June 18, 2020
    Inventors: Ryoma YOSHIOKA, Eiji TOYODA, Keiji TAKEMURA, Shigeyasu MORI
  • Patent number: 10411059
    Abstract: An aim of the present invention is to make it possible to achieve stable operation of thin film transistors in an imaging panel of an X-ray imaging system that uses an indirect conversion scheme. An imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and bias wiring line. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and irradiated by scintillation light. The bias wiring line is connected to the photoelectric conversion element and applies a reverse bias voltage to the photoelectric conversion element. The thin film transistor includes a semiconductor active layer and a gate electrode. The gate electrode is formed between the substrate and semiconductor active layer. The bias wiring line includes a portion that overlaps the gate electrode and semiconductor active layer as seen from the radiation direction of the scintillation light.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 10, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shigeyasu Mori, Kazuhide Tomiyasu
  • Patent number: 10386500
    Abstract: Provided is a technique that reduces patterning defects of data lines in an imaging panel and drain electrodes in thin film transistors without lowering the aperture ratio of the imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes, in each of the pixels, a conversion element that converts scintillation light to electric charge, and a thin film transistor connected to the gate line, data line, and conversion element. A drain electrode of the thin film transistor is formed such that edges of the drain electrode near the data line are more inside the pixel than edges of the conversion element near the data line.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: August 20, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Shigeyasu Mori
  • Patent number: 10381396
    Abstract: The present invention aims at inhibiting the occurrence of thinning or disconnecting of the bias wiring line in an imaging panel and X-ray imaging device, thereby inhibiting signal delays, signal transmission defects, and the like. A second contact hole electrically connecting an electrode of a photodiode to a bias wiring line penetrates a second interlayer insulating film and photosensitive resin layer. In the second contact hole, an area of a region where the photosensitive resin layer opens is smaller than an area of a region where the second interlayer insulating film opens.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 13, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Shigeyasu Mori
  • Patent number: 10353082
    Abstract: A second insulating film is disposed so as to cover a conversion element that includes a first insulating film, photodiode, and electrode. The second insulating film is made of a SiNxOy material, where x is greater than 0 and y is greater than or equal to 0. This makes it possible to provide a TFT and photodiode with excellent anti-moisture characteristics.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: July 16, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Shigeyasu Mori
  • Patent number: 10347687
    Abstract: An aim of the present invention is to improve the conversion efficiency of scintillation light into electric charge by a photoelectric conversion element in an imaging panel of an X-ray imaging system using an indirection conversion scheme. An imaging panel generates images based on scintillation light acquired from X-rays that have passed through a specimen. The imaging panel includes a substrate, thin film transistor, photoelectric conversion element, and reflective layer. The thin film transistor is formed on the substrate. The photoelectric conversion element is connected to the thin film transistor and converts incident scintillation light into electric charge. The entirety of a region of a light-receiving surface of the photoelectric conversion element where the scintillation light is incident overlaps the reflective layer as seen from the incident direction of the scintillation light. The reflective layer may be the drain electrode.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: July 9, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shigeyasu Mori, Kazuhide Tomiyasu
  • Patent number: 10330799
    Abstract: An X-ray image pickup system (10) includes an X-ray source (16), an image pickup panel (12), a scintillator (13), and an X-ray control unit (14E). The image pickup panel includes a photoelectric conversion element (26), a capacitor (50), a thin film transistor (24), and TFT control units (14A, 14B, 14F). To the photoelectric conversion element (26), scintillation light is projected. The capacitor (50) is connected to the photoelectric conversion element (26), and accumulates charges. The thin film transistor (24) is connected to the capacitor (50). The TFT control units (14A, 14B, 14F) control an operation of the thin film transistor (24). The thin film transistor (24) includes a semiconductor active layer (32) made of an oxide semiconductor. The X-ray control unit (14E) intermittently projects X-ray to the X-ray source (16). The TFT control units (14A, 14B, 14F) cause the thin film transistor (24) to operate when the X-ray is not projected, so as to read out the charges accumulated in the capacitor (50).
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 25, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Shigeyasu Mori, Kazuhide Tomiyasu
  • Patent number: 10304897
    Abstract: An aim of the present invention is to provide a technology that increases the aperture ratio of an imaging panel. The imaging panel captures scintillation light, which are X-rays that have passed through a specimen and been converted by a scintillator. The imaging panel includes a plurality of gate lines and a plurality of data lines. The imaging panel includes, in each of the pixels, a conversion element that converts scintillation light to electric charge, a thin film transistor connected to the gate line, data line, and conversion element, and a metal wiring line connecting to the conversion element and supplying a bias voltage to the conversion element. The metal wiring line is positioned generally parallel to the data line and is closer to the data line that connects to the thin film transistor than approximately the center in the extension direction of the gate line of the conversion element.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: May 28, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Kazuhide Tomiyasu, Shigeyasu Mori
  • Patent number: 10269831
    Abstract: A semiconductor device includes, a plurality of oxide semiconductor TFTs including a first gate electrode, a first insulating layer in contact with the first gate electrode, an oxide semiconductor layer opposing the first gate electrode via the first insulating layer, a source electrode and a drain electrode which are connected with the oxide semiconductor layer, and an organic insulating layer covering only some of the plurality of oxide semiconductor TFTs, wherein the plurality of oxide semiconductor TFTs include a first TFT which is covered with the organic insulating layer and a second TFT which is not covered with the organic insulating layer, and the second TFT includes a second gate electrode opposing the oxide semiconductor layer via a second insulating layer, the second gate electrode being arranged to overlap with at least a portion of the first gate electrode with the oxide semiconductor layer interposed therebetween.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: April 23, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Takao Saitoh, Seiji Kaneko, Yohsuke Kanzaki, Yutaka Takamaru, Keisuke Ide, Takuya Matsuo, Shigeyasu Mori, Hiroshi Matsukizono
  • Patent number: 10170826
    Abstract: A TFT substrate (101) including a plurality of antenna element regions (U) arranged on a dielectric substrate (1), the TFT substrate including a transmitting/receiving region including a plurality of antenna element regions, and a non-transmitting/receiving region located outside of the transmitting/receiving region, each of the plurality of antenna element regions (U) including: a thin film transistor (10); a first insulating layer (11) covering the thin film transistor and having a first opening (CH1) which exposes a drain electrode (7D) of the thin film transistor (10); and a patch electrode (15) formed on the first insulating layer (11) and in the first opening (CH1), and electrically connected to the drain electrode (7D) of the thin film transistor, wherein the patch electrode (15) includes a metal layer, and a thickness of the metal layer is greater than a thickness of a source electrode (7S) and the drain electrode (7D) of the thin film transistor.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: January 1, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Makoto Nakazawa, Takatoshi Orui, Shigeyasu Mori, Fumiki Nakano, Kiyoshi Minoura