Abstract: A storage system has a plurality of control modules for controlling a plurality of storage devices, which make mounting easier with maintaining low latency response even if the number of control modules increases. A plurality of storage devices are connected to the second interface of each control module using back end routers, so that redundancy for all the control modules to access all the storage devices is maintained. Also the control modules and the first switch units are connected by a serial bus, which has a small number of signals, constituting the interface by using the back panel. By this, mounting on the printed circuit board becomes possible.

Abstract: A sideband bus setting system in which multiple target devices (ICs) are communicably connected to a master device through a bus so as to set data to ICs mounted on an electronic device. The target device is provided with a target domain ID identifying a target domain-which is a subgroup of multiple target devices, and the master device is provided with the same target domain ID as that provided for the target device. The master device receives the target domain ID from the target device, and performs data-setting process to the target device when the target domain ID received from the target device coincides with the target domain ID provided for the master device. According to the above feature, the failure of the bus (for example, the failure of a sideband multiplexer) can be detected in advance, thereby preventing overlooking the improper data-setting operation.

Abstract: When a plurality of data blocks are divided into a plurality of frames and the divided frames are transmitted, every time a frame is received, a interim calculation result of a check code is updated using a transitional calculation result of the check code of the data block corresponding to the frame received and the data included in the frame. When a final calculation result of the check code of a data block is obtained, the calculation result is compared with the check code included in the data block.

Abstract: A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express switch. When a CPU unit, which is connected to the upstream port of a serial connect switch interconnecting the plurality of CPU units, is unable to operate, and the links between the CPU units and the switch cannot be established, a management controller in the switch unit is selected as a device of the upstream port.

Abstract: Before the link of each port of a switch provide with a plurality of ports for interconnecting a plurality of process nodes by a serial bus is established, it is checked whether each process node is mounted. Then, of the plurality of ports, a port to which one of mounted process nodes is connected is assigned as an upstream port and the other ports are assigned as downstream ports.

Abstract: A storage system has a plurality of control modules for controlling a storage device for accesses from a mainframe host and an open system host respectively supporting different protocols. An open channel adaptor and a mainframe channel adaptor are separately provided. The mainframe channel adaptor is connected to a plurality of control managers via front routers and performs parallel write access from the mainframe host for mirroring. In the write processing for the mainframe host, the connection is maintained until the completion of processing. In particular, even in case of a write miss, disk read processing can be performed in parallel, thus contributing to the high-speed processing in case of the write miss. Further, for an access from the open system host, a high throughput can be obtained.

Abstract: A storage system has a plurality of control modules for controlling a storage device for accesses from a mainframe host and an open system host respectively supporting different protocols. An open channel adaptor and a mainframe channel adaptor are separately provided. The mainframe channel adaptor is connected to a plurality of control managers via front routers and performs parallel write access from the mainframe host for mirroring. In the write processing for the mainframe host, the connection is maintained until the completion of processing. In particular, even in case of a write miss, disk read processing can be performed in parallel, thus contributing to the high-speed processing in case of the write miss. Further, for an access from the open system host, a high throughput can be obtained.

Abstract: A sideband bus setting system in which multiple target devices (ICs) are communicably connected to a master device through a bus so as to set data to ICs mounted on an electronic device. The target device is provided with a target domain ID identifying a target domain-which is a subgroup of multiple target devices, and the master device is provided with the same target domain ID as that provided for the target device. The master device receives the target domain ID from the target device, and performs data-setting process to the target device when the target domain ID received from the target device coincides with the target domain ID provided for the master device. According to the above feature, the failure of the bus (for example, the failure of a sideband multiplexer) can be detected in advance, thereby preventing overlooking the improper data-setting operation.

Abstract: A control device includes a control unit having operating modes having different heating values, and a fan unit including at least one fan for cooling the control unit in which the number of rotations varies depending on a voltage. The control unit includes a voltage supplying section for supplying different voltages corresponding to the operating modes. The fan unit includes a rotation control unit for rotating the fan with the highest voltage among the supplied different voltages.

Abstract: A computer system enable system operation by hiding the peculiarity of an upstream port of a switch in a computer system in which a plurality of CPU units are interconnected by a PCI Express switch. When a CPU unit, which is connected to the upstream port of a serial connect switch interconnecting the plurality of CPU units, is unable to operate, and the links between the CPU units and the switch cannot be established, a management controller in the switch unit is selected as a device of the upstream port.

Abstract: Before the link of each port of a switch provide with a plurality of ports for interconnecting a plurality of process nodes by a serial bus is established, it is checked whether each process node is mounted. Then, of the plurality of ports, a port to which one of mounted process nodes is connected is assigned as an upstream port and the other ports are assigned as downstream ports.

Abstract: A storage system has a plurality of control modules for controlling a plurality of storage devices, which make mounting easier with maintaining low latency response even if the number of control modules increases. A plurality of storage devices are connected to the second interface of each control module using back end routers, so that redundancy for all the control modules to access all the storage devices is maintained. Also the control modules and the first switch units are connected by a serial bus, which has a small number of signals, constituting the interface by using the back panel. By this, mounting on the printed circuit board becomes possible.

Abstract: When a plurality of data blocks are divided into a plurality of frames and the divided frames are transmitted, every time a frame is received, a interim calculation result of a check code is updated using a transitional calculation result of the check code of the data block corresponding to the frame received and the data included in the frame. When a final calculation result of the check code of a data block is obtained, the calculation result is compared with the check code included in the data block.