Patents by Inventor Shigeyuki Horie

Shigeyuki Horie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7719852
    Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: May 18, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Yutaka Ota, Jun Nishikawa
  • Patent number: 7379288
    Abstract: The monolithic ceramic electronic component includes a first external electrode 5, a second external electrode 6, and a ceramic sintered compact 4 including internal electrodes 2 and 3, the first and second external electrodes 5 and 6 being disposed on both end faces 4a and 4b of the ceramic sintered compact 4. The first and second external electrodes 5 and 6 have a multilayer structure in which sintered electrode layers 5a and 6a, intermediate electroplated layers 5b and 6b, and plated layers 5c and 6c are arranged in that order. Exposed surface regions 7a of insulating oxides 7 are exposed from the outer faces of the sintered electrode layers 5a and 6a, the oxides 7 being derived from a glass frit contained in the sintered electrode layers. Metals 8 are deposited on the exposed surface regions 7a and the intermediate electroplated layers 5b and 6b are then formed by electroplating.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: May 27, 2008
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Tomohiro Dozen, Takashi Noji, Tatsuo Furusawa, Takaaki Kawai
  • Publication number: 20080118721
    Abstract: A high-reliability electronic component without reduction in insulation resistance under high-temperature and high-humidity conditions has satisfactory solderability of external electrodes. The electronic component includes a main body and external electrodes disposed on surfaces of the main body, the external electrodes include underlying electrode layers each containing a metal, alloy layers each disposed on the corresponding underlying electrode layer, Ni plating layers each disposed on the corresponding alloy layer, Ni oxide layers each disposed on the corresponding Ni plating layers, and upper plating layers each disposed on the corresponding Ni oxide layer, each Ni oxide layer having a thickness of about 150 nm or less, and each Ni plating layer having an average particle size of Ni particles of about 2 ?m or more. To form the Ni plating layers having reduced grain boundaries, heat treatment is performed at about 500° C. to about 900° C.
    Type: Application
    Filed: January 3, 2008
    Publication date: May 22, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Shigeyuki HORIE, Yutaka OTA, Jun NISHIKAWA
  • Publication number: 20070109718
    Abstract: The monolithic ceramic electronic component includes a first external electrode 5, a second external electrode 6, and a ceramic sintered compact 4 including internal electrodes 2 and 3, the first and second external electrodes 5 and 6 being disposed on both end faces 4a and 4b of the ceramic sintered compact 4. The first and second external electrodes 5 and 6 have a multilayer structure in which sintered electrode layers 5a and 6a, intermediate electroplated layers 5b and 6b, and plated layers 5c and 6c are arranged in that order. Exposed surface regions 7a of insulating oxides 7 are exposed from the outer faces of the sintered electrode layers 5a and 6a, the oxides 7 being derived from a glass frit contained in the sintered electrode layers. Metals 8 are deposited on the exposed surface regions 7a and the intermediate electroplated layers 5b and 6b are then formed by electroplating.
    Type: Application
    Filed: February 1, 2005
    Publication date: May 17, 2007
    Inventors: Shigeyuki Horie, Tomohiro Dozen, Takashi Noji, Tatsuo Furusawa, Takaaki Kawai
  • Patent number: 6361676
    Abstract: A technique for manufacturing electronic parts uses barrel plating to plate films on external electrodes of the electronic parts with small thickness variation of the plated films. The technique comprises disposing a plurality of non-spherical conductive elements in a plating barrel, disposing a plurality of electronic parts in the plating barrel, and rotating the plating barrel to form the plated films on the external electrodes of the electronic parts.
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: March 26, 2002
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Takao Hosokawa
  • Patent number: 5508562
    Abstract: A chip type electronic part has an outer electrode structure appropriate mainly for reflow soldering.An outermost layer of the outer electrode, provided at both end portions of the chip type electronic part, is to be soldered and made of a metal having a solidus temperature lower than 183.degree. C. and a difference not smaller than 10.degree. C., or more preferably not smaller than 30.degree. C., between its liquidus temperature and its solidus temperature, and is formed of a plating coat. The above-mentioned arrangement allows reflow soldering for the mounting of the chip type electronic part onto a substrate to be achieved at a low temperature while preventing the harmful influences of high-temperature soldering, and prevents the tombstone phenomenon in the soldering process.
    Type: Grant
    Filed: December 9, 1994
    Date of Patent: April 16, 1996
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Shigeyuki Horie, Kimiharu Anao