Abstract: A magnetic-field detection microcomputer includes: a magnetic-field detection device; a differential amplifier; a variable voltage circuit which generates a reference voltage that is variable; a comparator which compares an output from the differential amplifier with the reference voltage; a register which outputs a voltage control value to the variable voltage circuit; a ROM which previously store a first table in which a magnetic-field intensity and the voltage control value are associated with each other; and a CPU which sets, to the register, the voltage control value, and determines presence or absence of the magnetic-field intensity associated with the voltage control value based on a result of the comparison by the comparator and the first table.

Abstract: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area.

Abstract: A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.

Abstract: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area.

Abstract: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area.

Abstract: A combination memory device including a static random access memory (SRAM) and a read only memory (ROM) comprises first memory cells and second memory cells arranged in rows and columns, in which each of the first memory cells includes an SRAM cell and a ROM cell and is arranged adjacent to at least one of the second memory cells, and each of the second memory cells includes an SRAM cell and does not include a ROM cell.

Abstract: A semiconductor device in which size reduction is possible without functional devices below pads being damaged by stress. The semiconductor device has a plurality of pads above a semiconductor substrate as terminals for external connection. A plurality of dual use pads which are used in both a probing test and assembly are provided in a first area above a main surface of the semiconductor substrate, an application of pressure by a probe during the probing test being permitted in the first area, and a plurality of assembly pads which are not used in the probing test are provided in a second area above the main surface of the semiconductor substrate, the application of pressure by the probe during the probing test being not permitted in the second area.

Abstract: The semiconductor integrated circuit includes: a first electrode; a transistor, having a second electrode, formed on a semiconductor substrate; and third and fourth electrodes formed in a same metal layer. The first electrode is connected with a diffusion region constituting the transistor. The second electrode constitutes the gate of the transistor. The third and fourth electrodes are respectively in a comb shape and formed to at least partly overlie the transistor. None of the first to fourth electrodes is connected with any of the other electrodes.

Abstract: An analog-digital converter includes an analog switch on a semiconductor substrate, the analog switch having a P-channel transistor and an N-channel transistor; and a capacitive element having a first electrode and a second electrode. The first electrode and the second electrode are formed in a region in a layer different from a layer of the analog switch, the region extending over the analog switch. The first electrode and the second electrode have a comb-shaped pattern different from an arrangement pattern of the source regions and the drain regions of the P-channel transistor and the N-channel transistor.

Abstract: An analog-digital converter includes an analog switch on a semiconductor substrate, the analog switch having a P-channel transistor and an N-channel transistor; and a capacitive element having a first electrode and a second electrode. The first electrode and the second electrode are formed in a region in a layer different from a layer of the analog switch, the region extending over the analog switch. The first electrode and the second electrode have a comb-shaped pattern different from an arrangement pattern of the source regions and the drain regions of the P-channel transistor and the N-channel transistor.

Abstract: According to a semiconductor device of the present invention, a layer of an electric insulator is provided on a semiconductor substrate. A connection pad having a part exposed to a layer surface is provided in the layer. A transistor structure opposed to the connection pad across the electric insulator is provided on the semiconductor substrate. The transistor structure comprises a polysilicon gate opposed to the connection pad across the insulator in the thickness direction of the layer, and a diffusion region provided outside of the respective opposed side edges of the polysilicon gate on a plane where the polysilicon gate is formed. As a result, according to the present invention, a power supply noise between I/O is absorbed and there is provided an excellent effect on an EMI and an EMS especially.

Abstract: According to a semiconductor device of the present invention, a layer of an electric insulator is provided on a semiconductor substrate. A connection pad having a part exposed to a layer surface is provided in the layer. A transistor structure opposed to the connection pad across the electric insulator is provided on the semiconductor substrate. The transistor structure comprises a polysilicon gate opposed to the connection pad across the insulator in the thickness direction of the layer, and a diffusion region provided outside of the respective opposed side edges of the polysilicon gate on a plane where the polysilicon gate is formed. As a result, according to the present invention, a power supply noise between I/O is absorbed and there is provided an excellent effect on an EMI and an EMS especially.

Abstract: When an error is found in a program of the microcomputer, there are stored in a writable memory change address data of an address of a wrong instruction to be subjected to modification or insertion in the read-only memory, change instruction codes of modification or insertion for replacement of the wrong instruction, and a control code controlling a second program counter. When the contents of the program counter match the change address data stored in the writable memory, the program data in the writable memory is executed in place of the wrong instruction in the read-only memory according to the control code controlling the second program counter. Consequently, even when a bug is found in the program, a program replacement and/or insertion can be easily achieved and it is unnecessary to discard the final product on which the program is developed through a mask. Moreover, the program can be easily changed from an external device.