Patents by Inventor Shigeyuki Nakazawa
Shigeyuki Nakazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11289135Abstract: Apparatuses for controlling precharge timings in a semiconductor device are described. An example apparatus includes first and second memory and a precharge timing circuit. The first memory includes a first memory bank including a first data line and a second memory bank including a second data line. The second memory includes a third memory bank including a third data line and a fourth memory bank memory bank including a fourth data line. The precharge timing circuit provides first, second, third and fourth precharge activation signals. The first, second, third and fourth precharge activation signals activate precharge of the first, second, third and fourth data lines, respectively. The precharge timing circuit provides the first and second precharge activation signals at different times from each other. The precharge timing circuit provides the third and fourth precharge activation signals at different times from each other.Type: GrantFiled: December 8, 2020Date of Patent: March 29, 2022Assignee: Micron Technology, Inc.Inventor: Shigeyuki Nakazawa
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Patent number: 9466562Abstract: Disclosed herein is a semiconductor chip that includes: a plurality of penetration electrodes each penetrating between main and back surfaces of the semiconductor chip, the penetration electrodes including a plurality of first penetration electrodes, a second penetration electrode and a third penetration electrode; and a wiring configured to intersect with a plurality of regions, each of the regions being defined as a region between corresponding two of the first penetration electrodes, one end of the wiring being coupled to the second penetration electrode, the other end of the wiring being coupled to the third penetration electrode.Type: GrantFiled: December 19, 2012Date of Patent: October 11, 2016Assignee: PS4 Luxco S.a.r.l.Inventors: Shigeyuki Nakazawa, Toru Ishikawa
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Patent number: 8525578Abstract: Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.Type: GrantFiled: January 25, 2012Date of Patent: September 3, 2013Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20120194260Abstract: Such a device is disclosed that includes a first ladder fuse for which blowing points are arranged at a first coordinate and a second ladder fuse for which blowing points are arranged at a second coordinate. When adjustment data for adjusting circuit characteristics is within a first range, a trimming operation is performed on both the first and second ladder fuses, and when the adjustment data for adjusting the circuit characteristics is within a second range, the trimming operation is performed on the second ladder fuse without performing the trimming operation on the first ladder fuse. This configuration eliminates a necessity of irradiation on the first ladder fuse with a laser when the adjustment data is within the second range.Type: ApplicationFiled: January 25, 2012Publication date: August 2, 2012Applicant: ELPIDA MEMORY, INC.Inventor: Shigeyuki NAKAZAWA
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Patent number: 8040751Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: GrantFiled: June 29, 2009Date of Patent: October 18, 2011Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Patent number: 7990789Abstract: A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.Type: GrantFiled: January 29, 2009Date of Patent: August 2, 2011Assignee: Elpida Memory, Inc.Inventors: Shigeyuki Nakazawa, Toru Ishikawa
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Patent number: 7956470Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.Type: GrantFiled: September 27, 2006Date of Patent: June 7, 2011Assignee: Elpida Memory, Inc.Inventors: Satoshi Isa, Mitsuaki Katagiri, Toru Chonan, Shigeyuki Nakazawa
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Patent number: 7706166Abstract: A semiconductor memory device has first and second AF programming circuits having low and high AF programming threshold power supply voltages, respectively. In a process where a large majority of programming is carried out in the semiconductor memory device alone, the second AF programming circuit is used. In a module process where semiconductor devices having low withstand voltages are mounted in a module, the first AF programming circuit is used.Type: GrantFiled: April 24, 2007Date of Patent: April 27, 2010Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20090262590Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: ApplicationFiled: June 29, 2009Publication date: October 22, 2009Applicant: ELPIDA MEMORY, INC.Inventor: Shigeyuki Nakazawa
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Patent number: 7573778Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: GrantFiled: July 15, 2008Date of Patent: August 11, 2009Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20090190411Abstract: A semiconductor memory device, in which a plurality of data output lines are commonly used by a plurality of banks, includes a plurality of gate circuits each of which are provided at each intermediate position of the plurality of the data output lines, and is controlled to be turned on during a normal operation mode and to be turned off at least when reading data during a parallel test mode, and a comparator circuit that inputs in parallel and compares a signal of each separated part of the each data output line separated by the plurality of the gate circuit being turned off.Type: ApplicationFiled: January 29, 2009Publication date: July 30, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Shigeyuki Nakazawa, Toru Ishikawa
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Publication number: 20090021993Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: ApplicationFiled: July 15, 2008Publication date: January 22, 2009Applicant: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Patent number: 7414914Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: GrantFiled: October 23, 2006Date of Patent: August 19, 2008Assignee: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20070253236Abstract: A semiconductor memory device has first and second AF programming circuits having low and high AF programming threshold power supply voltages, respectively. In a process where a large majority of programming is carried out in the semiconductor memory device alone, the second AF programming circuit is used. In a module process where semiconductor devices having low withstand voltages are mounted in a module, the first AF programming circuit is used.Type: ApplicationFiled: April 24, 2007Publication date: November 1, 2007Applicant: Elpida Memory, Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20070085214Abstract: A semiconductor device has a semiconductor chip which is usable as any one of 4-bit, 8-bit, and 16-bit structure devices, and a package for packaging the semiconductor chip. The semiconductor chip has first and second DQ pad groups of DQ system pads for said 16-bit structure device. The first DQ pad group is arranged in a first area at a vicinity of a middle part of a surface of the semiconductor chip while the second DQ pad group is arranged in a second area at an outer side of the first area on the surface. An additional pad necessary as one of DQ system pads for the 8-bit structure device except for pads included in the second DQ pad group is formed in the second area.Type: ApplicationFiled: September 27, 2006Publication date: April 19, 2007Inventors: Satoshi Isa, Mitsuaki Katagiri, Toru Chonan, Shigeyuki Nakazawa
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Publication number: 20070058476Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: ApplicationFiled: October 23, 2006Publication date: March 15, 2007Inventor: Shigeyuki Nakazawa
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Patent number: 7151713Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: GrantFiled: May 27, 2003Date of Patent: December 19, 2006Assignee: Elpida Memory Inc.Inventor: Shigeyuki Nakazawa
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Publication number: 20030226064Abstract: A semiconductor memory device has a command decoder responsive to a plurality of commands to set the semiconductor memory device to a normal mode, for generating control signals corresponding to the commands, respectively, and a row address prelatch circuit for holding a row address except for a bank address input together with a precharge command, and outputting the row address to a row address latch circuit, when the semiconductor memory device is in a test mode. The row address latch circuit holds the row address output from the row address prelatch circuit in synchronism with a control signal which is generated when an active command is input. The column address latch circuit holds the column address which has already been input when the active command is input, in synchronism with a control signal which is generated when either a read command or a write command is input.Type: ApplicationFiled: May 27, 2003Publication date: December 4, 2003Inventor: Shigeyuki Nakazawa
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Patent number: 6545922Abstract: A memory cell array is provided to a semiconductor memory device, and a plurality of memory cells composes a column in the memory cell array. The plurality of memory cells are commonly connected to a plurality of bit line pairs. The plurality of bit line pairs are commonly connected to an I/O line pair. A pre-charge circuit is also provided to the semiconductor memory device. The pre-charge circuit pre-charges the I/O line pair. The pre-charge circuit has a selection circuit within selects a pre-charge level of the I/O line pair from among a plurality of voltage levels.Type: GrantFiled: December 28, 2000Date of Patent: April 8, 2003Assignee: NEC CorporationInventor: Shigeyuki Nakazawa
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Patent number: 6333888Abstract: A semiconductor memory device capable of normally executing a refresh counter test with simplified circuit configurations and wiring is provided. According to the semiconductor memory device of the present invention, column decoders of all banks are activated, at a time of executing a refresh counter test, based on a write command or read command supplied after a refresh command has been supplied.Type: GrantFiled: April 20, 2000Date of Patent: December 25, 2001Assignee: NEC CorporationInventor: Shigeyuki Nakazawa