Patents by Inventor Shigeyuki SAKUMA
Shigeyuki SAKUMA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11152247Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: GrantFiled: June 19, 2020Date of Patent: October 19, 2021Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Publication number: 20200321239Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: ApplicationFiled: June 19, 2020Publication date: October 8, 2020Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Patent number: 10714375Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: GrantFiled: November 30, 2016Date of Patent: July 14, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Patent number: 10541299Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.Type: GrantFiled: November 30, 2016Date of Patent: January 21, 2020Assignee: SEIKO EPSON CORPORATIONInventors: Kazunobu Kuwazawa, Shigeyuki Sakuma, Hiroaki Nitta, Mitsuo Sekisawa, Takehiro Endo
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Publication number: 20190158021Abstract: This temperature-compensated crystal oscillator includes: a crystal resonator; first and second MOS-type variable capacitance elements, each having one end electrically connected to first or second electrodes of the crystal resonator; and a temperature compensation circuit that applies a temperature compensation voltage, which changes in accordance with a temperature, to other ends of the first and second MOS-type variable capacitance elements. The first MOS-type variable capacitance element includes a first back gate provided within a semiconductor substrate, and an N-type first gate electrode provided above the first back gate with an insulating film interposed therebetween; and the second MOS-type variable capacitance element includes a second back gate provided within the semiconductor substrate and having the same conductivity type as the first back gate, and a P-type second gate electrode provided above the second back gate with an insulating film interposed therebetween.Type: ApplicationFiled: November 21, 2018Publication date: May 23, 2019Applicant: SEIKO EPSON CORPORATIONInventor: Shigeyuki SAKUMA
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Publication number: 20170170053Abstract: A semiconductor device is provided in which a zener diode having a desired breakdown voltage and a capacitor in which voltage dependence of capacitance is reduced are mounted together, and various circuits are realized. The semiconductor device includes: a semiconductor layer; a first conductivity type well that is arranged in a first region of the semiconductor layer; a first conductivity type first impurity diffusion region that is arranged in the well; a first conductivity type second impurity diffusion region that is arranged in a second region of the semiconductor layer; an insulating film that is arranged on the second impurity diffusion region; an electrode that is arranged on the insulating film; and a second conductivity type third impurity diffusion region that is arranged at least on the first impurity diffusion region.Type: ApplicationFiled: November 30, 2016Publication date: June 15, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Publication number: 20170170262Abstract: A semiconductor device includes a first conductivity type semiconductor substrate, a second conductivity type first and second buried diffusion layers that are arranged in the semiconductor substrate, a semiconductor layer arranged on the semiconductor substrate, a second conductivity type first impurity diffusion region that is arranged in the semiconductor layer, a second conductivity type second impurity diffusion region that is arranged, in the semiconductor layer, on the second buried diffusion layer, a second conductivity type first well that is arranged in a first region of the semiconductor layer, a first conductivity type second well that is arranged, in the semiconductor layer, in a second region, a first conductivity type third and fourth impurity diffusion regions that are arranged in the first well, and a first conductivity type fifth impurity diffusion region that is arranged in the second well.Type: ApplicationFiled: November 30, 2016Publication date: June 15, 2017Applicant: SEIKO EPSON CORPORATIONInventors: Kazunobu KUWAZAWA, Shigeyuki SAKUMA, Hiroaki NITTA, Mitsuo SEKISAWA, Takehiro ENDO
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Patent number: 9190470Abstract: A semiconductor device including field insulating films and having first corner portions, provided on a P-type epitaxial growth layer; an N?-type cathode that is provided in the P-type epitaxial growth layer and is located on the inner sides of the field insulating films; and a P?-type anode that is formed on the cathode so as to be in contact with the cathode and covers the first corner portions provided on the inner sides of the field insulating films, wherein the junction between the cathode and the anode serves as a PN junction of the diode, and the PN junction is spaced apart from the first corner portions.Type: GrantFiled: November 5, 2014Date of Patent: November 17, 2015Assignee: SEIKO EPSON CORPORATIONInventor: Shigeyuki Sakuma
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Publication number: 20150123237Abstract: A semiconductor device including field insulating films and having first corner portions, provided on a P-type epitaxial growth layer; an N?-type cathode that is provided in the P-type epitaxial growth layer and is located on the inner sides of the field insulating films; and a P?-type anode that is formed on the cathode so as to be in contact with the cathode and covers the first corner portions provided on the inner sides of the field insulating films, wherein the junction between the cathode and the anode serves as a PN junction of the diode, and the PN junction is spaced apart from the first corner portions.Type: ApplicationFiled: November 5, 2014Publication date: May 7, 2015Inventor: Shigeyuki SAKUMA