Patents by Inventor Shigeyuki Sugihara
Shigeyuki Sugihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11971632Abstract: The present invention provides a dimming panel sequentially including: a first substrate; a liquid crystal layer; and a second substrate, the first substrate sequentially including an insulating substrate, a first electrode, a first insulator layer, and a second electrode, the second electrode including, in a plan view, linear electrodes parallel to each other with slit regions in between, and bridge electrodes each of which is disposed in one of the slit regions and is connecting two adjacent linear electrodes, the bridge electrodes including a first bridge electrode in a first slit region, a second bridge electrode in a second slit region adjacent to the first slit region, and a third bridge electrode in a third slit region adjacent to the second slit region, the first bridge electrode, the second bridge electrode, and the third bridge electrode being discrete from one another.Type: GrantFiled: August 1, 2022Date of Patent: April 30, 2024Assignee: SHARP KABUSHIKI KAISHAInventors: Fumikazu Shimoshikiryoh, Shigeyuki Yamada, Toshinori Sugihara, Takehisa Yoshida
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Patent number: 10629606Abstract: A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.Type: GrantFiled: November 7, 2017Date of Patent: April 21, 2020Assignee: SANDISK TECHNOLOGIES LLCInventors: Nobutoshi Sugawara, Shigeyuki Sugihara
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Patent number: 10403639Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: GrantFiled: November 20, 2017Date of Patent: September 3, 2019Assignee: SANDISK TECHNOLOGIES LLCInventors: Takashi Orimoto, James Kai, Sayako Nagamine, Takaaki Iwai, Shigeyuki Sugihara, Shuji Minagawa
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Publication number: 20190139974Abstract: A plurality of horizontal top surfaces that are vertically offset is formed on a substrate. An alternating stack of insulating layers and spacer material layers is formed and patterned to provide a plurality of staircase regions that are laterally spaced apart and overlies a respective one of the plurality of horizontal top surfaces of the substrate. Memory stack structures are formed through the alternating stack. The spacer material layers are formed as, or are replaced with, electrically conductive layers. A set of contact via cavities are formed over the electrically conductive layers.Type: ApplicationFiled: November 7, 2017Publication date: May 9, 2019Inventors: Nobutoshi SUGAWARA, Shigeyuki SUGIHARA
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Publication number: 20190027489Abstract: An array of memory stack structures extends through an alternating stack of insulating layers and electrically conductive layers over a substrate. An array of drain select level assemblies including cylindrical electrode portions is formed over the alternating stack with the same periodicity as the array of memory stack structures. A drain select level isolation strip including dielectric materials can be formed between a neighboring pair of drain select level assemblies employing the drain select level assemblies as a self-aligning template. Alternatively, cylindrical electrode portions can be formed around an upper portion of each memory stack structure. Strip electrode portions are formed on the cylindrical electrode portions after formation of the drain select level isolation strip.Type: ApplicationFiled: November 20, 2017Publication date: January 24, 2019Inventors: Takashi ORIMOTO, James KAI, Sayako Najamine, Takaaki Iwai, Shigeyuki Sugihara, Shuji Minagawa
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Patent number: 8692330Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.Type: GrantFiled: June 21, 2012Date of Patent: April 8, 2014Assignee: Semiconductor Components Industries, LLCInventors: Yuzo Otsuru, Yasuhiro Takeda, Shigeyuki Sugihara, Shinya Inoue
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Publication number: 20120326235Abstract: A semiconductor device equally turns on the parasitic bipolar transistors in the finger portions of the finger form source and drain electrodes when a surge voltage is applied, even with the P+ type contact layer surrounding the N+ type source layers and the N+ type drain layers connected to the finger form source and drain electrodes. A P+ type contact layer surrounds N+ type source layers and N+ type drain layers. Metal silicide layers are formed on the N+ type source layers, the N+ type drain layers, and a portion of the P+ type contact layer. Finger form source electrodes, finger form drain electrodes, and a P+ type contact electrode surrounding these finger form electrodes are formed, being connected to the metal silicide layers respectively through contact holes formed in an interlayer insulation film deposited on the metal silicide layers.Type: ApplicationFiled: June 21, 2012Publication date: December 27, 2012Applicant: Semiconductor Components Industries, LLCInventors: Yuzo OTSURU, Yasuhiro Takeda, Shigeyuki Sugihara, Shinya Inoue
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Patent number: 7468303Abstract: Junction leakage in a medium voltage MOS transistor having a silicide structure is prevented. A titanium layer is formed by sputtering titanium over the entire surface of a semiconductor substrate. A gate electrode makes contact with the titanium layer through an opening and P+-type diffusion layers make contact with the titanium layer through openings. In subsequent heat treatment, portions of the titanium layer contacting the gate electrode or each of the P+-type diffusion layers are changed into silicide, forming titanium silicide layers on the gate electrode and the P+-type diffusion layers. Then the rest of the titanium layer, which is on the silicide block layer and not changed into silicide, is removed by wet-etching.Type: GrantFiled: October 1, 2004Date of Patent: December 23, 2008Assignee: Sanyo Electric Co., Ltd.Inventor: Shigeyuki Sugihara
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Publication number: 20050161767Abstract: Junction leakage in a diffused resistor having a silicide structure is prevented. A titanium layer is formed by sputtering titanium over an entire surface of a semiconductor substrate. A P+-type diffusion layer makes contact with the titanium layer through an opening. Subsequent heat treatment changes portions of the titanium layer, which are in contact with the P+-type diffusion layer, into silicide to form a titanium silicide layer on a surface of the P+-type diffusion layer. Then the rest of the titanium layer, which is not changed into silicide, is removed by wet-etching.Type: ApplicationFiled: December 22, 2004Publication date: July 28, 2005Applicant: Sanyo Electric Co., Ltd.Inventor: Shigeyuki Sugihara
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Publication number: 20050104135Abstract: Junction leakage in a medium voltage MOS transistor having a silicide structure is prevented. A titanium layer is formed by sputtering titanium over the entire surface of a semiconductor substrate. A gate electrode makes contact with the titanium layer through an opening and P+-type diffusion layers make contact with the titanium layer through openings. In subsequent heat treatment, portions of the titanium layer contacting the gate electrode or each of the P+-type diffusion layers are changed into silicide, forming titanium silicide layers on the gate electrode and the P+-type diffusion layers. Then the rest of the titanium layer, which is on the silicide block layer and not changed into silicide, is removed by wet-etching.Type: ApplicationFiled: October 1, 2004Publication date: May 19, 2005Applicant: Sanyo Electric Co., Ltd.Inventor: Shigeyuki Sugihara