Patents by Inventor Shigeyuki Takeuchi
Shigeyuki Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11965510Abstract: A compressor body includes a compression mechanism including a screw rotor that compresses gas, a casing that accommodates the compression mechanism and defines a compression working chambers therein, a suction side bearing that rotatably supports the screw rotor, a bearing chamber that accommodates the suction side bearing, and a liquid supply port that communicates with the compression working chambers and supplies liquid supplied from the outside of the casing into the compression working chambers. The casing has an internal liquid supply flow path that extends from a discharge side of the compression working chambers as an upstream side to a suction side of the compression working chambers as a downstream side and that supplies the liquid to the liquid supply port. The internal liquid supply flow path has a downstream portion reaching the bearing chamber and supplies the liquid to the suction side bearing.Type: GrantFiled: September 28, 2020Date of Patent: April 23, 2024Assignee: Hitachi Industrial Equipment Systems Co., Ltd.Inventors: Shigeyuki Yorikane, Masahiko Takano, Kenji Morita, Yoshitaka Takeuchi
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Patent number: 10978446Abstract: Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device (100) includes a semiconductor element (50) and a control element (150) arranged on a front surface (50a) of the semiconductor element (50). The semiconductor element (50) includes a semiconductor substrate (SB) including a first region AR1 and a second region AR2 adjacent to each other, a first MOS transistor (Tr1) provided is the first region (AR1), and a second MOS transistor (Tr2) provided in the second region (AR2). A first drain region (3a) of the first MOS transistor (Tr1) is connected to a second drain region (3b) of the second MOS transistor (Tr2). The control element (150) turns on and off the first MOS transistor (Tr1) and the second MOS transistor (Tr2).Type: GrantFiled: July 26, 2019Date of Patent: April 13, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventors: Morio Iwamizu, Shigeyuki Takeuchi
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Publication number: 20200127558Abstract: A load driver circuit including an oscillator circuit configured to generate a clock, a charge pump circuit configured to receive the clock and operate according to the clock, and a boosting-capability control circuit configured to control the boosting capability of the charge pump circuit according to a value of an output voltage of the charge pump circuit.Type: ApplicationFiled: September 30, 2019Publication date: April 23, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Kenji FUJITSU, Morio IWAMIZU, Shigeyuki TAKEUCHI
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Publication number: 20200091139Abstract: Provided is a semiconductor device capable of reducing a mounting area. A semiconductor device (100) includes a semiconductor element (50) and a control element (150) arranged on a front surface (50a) of the semiconductor element (50). The semiconductor element (50) includes a semiconductor substrate (SB) including a first region AR1 and a second region AR2 adjacent to each other, a first MOS transistor (Tr1) provided is the first region (AR1), and a second MOS transistor (Tr2) provided in the second region (AR2). A first drain region (3a) of the first MOS transistor (Tr1) is connected to a second drain region (3b) of the second MOS transistor (Tr2). The control element (150) turns on and off the first MOS transistor (Tr1) and the second MOS transistor (Tr2).Type: ApplicationFiled: July 26, 2019Publication date: March 19, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Morio IWAMIZU, Shigeyuki Takeuchi
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Patent number: 10103539Abstract: A semiconductor device, including a main transistor configured to supply power from a power source to a load, and a current limiting device including a control transistor. The current limiting device is configured to detect that the current flowing from the main transistor is an overcurrent, and to limit the current upon determining that the current is equal to or greater than a current limit value, and an operating voltage of the control transistor is equal to or greater than a current limiting activation voltage. The current limit value is a threshold for determining whether the current is greater than an operating current of the main transistor for the load to operate in a steady state. The current limiting activation voltage is a sum of a correction voltage and a predetermined threshold voltage at the gate of the control transistor when the current rises to the current limit value.Type: GrantFiled: November 6, 2015Date of Patent: October 16, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Morio Iwamizu, Shigeyuki Takeuchi
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Publication number: 20160181792Abstract: A semiconductor device, including a main transistor configured to supply power from a power source to a load, and a current limiting device including a control transistor. The current limiting device is configured to detect that the current flowing from the main transistor is an overcurrent, and to limit the current upon determining that the current is equal to or greater than a current limit value, and an operating voltage of the control transistor is equal to or greater than a current limiting activation voltage. The current limit value is a threshold for determining whether the current is greater than an operating current of the main transistor for the load to operate in a steady state. The current limiting activation voltage is a sum of a correction voltage and a predetermined threshold voltage at the gate of the control transistor when the current rises to the current limit value.Type: ApplicationFiled: November 6, 2015Publication date: June 23, 2016Applicant: FUJI ELECTRIC CO., LTD.Inventors: Morio IWAMIZU, Shigeyuki TAKEUCHI
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Patent number: 8633723Abstract: A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.Type: GrantFiled: February 10, 2011Date of Patent: January 21, 2014Assignee: Fuji Electric Co., Ltd.Inventor: Shigeyuki Takeuchi
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Publication number: 20110198587Abstract: A semiconductor apparatus according to aspects of the invention includes a power MOSFET including a main MOSFET and sensing MOSFET's. The main MOSFET and the sensing MOSFET's are formed on a semiconductor substrate, and a sensing MOSFET is selected for changing the sensing ratio and further for confining the sensing ratio variations within a certain narrow range stably from a low main current range to a high main current range. A semiconductor apparatus according to aspects of the invention facilitates reducing the manufacturing costs thereof, obviating the cumbersomeness caused in the use thereof, and confining the sensing ratio variations within a certain narrow range stably.Type: ApplicationFiled: February 10, 2011Publication date: August 18, 2011Applicant: C/O FUJI ELECTRIC SYSTEMS CO., LTDInventor: Shigeyuki TAKEUCHI
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Publication number: 20110123671Abstract: The invention provides an additive for livestock feed and ingredients for a feed composition for livestock to improve the feed conversion ratio and the body weight gain efficiency by increasing the feed intake of livestock. The feed intake of livestock can be increased by providing the additive in the livestock feed, which includes monosodium L-glutamate and L-tryptophan, and wherein the mass ratio of free monosodium L-glutamate (provided that all converted into monosodium L-glutamate monohydrate) and free L-tryptophan (GLU/TRP ratio) is from 0.5 to 30.Type: ApplicationFiled: February 4, 2011Publication date: May 26, 2011Inventors: Makoto Miura, Kazuki Nakagawa, Shigeyuki Takeuchi, Kazumasa Watanabe
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Patent number: 7018194Abstract: A powder molding apparatus comprises a mold comprising a die having a powder molding space and upper and lower punch units, and a compression driving mechanism for performing compression molding by driving the upper and lower punch units independently, wherein molded articles formed by the compression molding are held by engaging lower first and second punches serving as a formed article holding mechanism at the time of transporting the molded articles. Thus, the molded articles can be prevented from falling or shifting while being transported between stages, thereby providing a powder molding apparatus capable of high speeds.Type: GrantFiled: December 4, 2001Date of Patent: March 28, 2006Assignee: Murata Manufacturing Co., Ltd.Inventors: Makoto Kitamura, Shigeki Takahashi, Tadanori Higaki, Yoshio Oda, Kouki Sai, Shigeyuki Takeuchi
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Patent number: 6462382Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: GrantFiled: March 19, 2001Date of Patent: October 8, 2002Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
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Publication number: 20020090412Abstract: A powder molding apparatus comprises a mold comprising a die having a powder molding space and upper and lower punch units, and a compression driving mechanism for performing compression molding by driving the upper and lower punch units independently, wherein molded articles formed by the compression molding are held by engaging lower first and second punches serving as a formed article holding mechanism at the time of transporting the molded articles. Thus, the molded articles can be prevented from falling or shifting while being transported between stages, thereby providing a powder molding apparatus capable of high speeds.Type: ApplicationFiled: December 4, 2001Publication date: July 11, 2002Inventors: Makoto Kitamura, Shigeki Takahashi, Tadanori Higaki, Yoshio Oda, Kouki Sai, Shigeyuki Takeuchi
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Publication number: 20010010379Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: ApplicationFiled: March 19, 2001Publication date: August 2, 2001Applicant: Fuji Electric, Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
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Publication number: 20010008041Abstract: A method for manufacturing an insert-resin-molded product prevents resin burrs from being generated. The method includes the steps of: preparing a resin-molding mold having a cavity having an inner wall including a recess formed therein; preparing a metallic member to be placed in the cavity of the resin-molding mold so as to be integrally molded with resin, the member having a metallic part to be fit into a recess of the resin-molding mold; placing the metallic member in the cavity of the resin-molding mold and fitting the metallic part of the metallic member into the recess of the resin-molding mold; and injecting resin into the cavity of the resin-molding mold to integrally insert-resin-mold with the metallic member.Type: ApplicationFiled: March 8, 2001Publication date: July 19, 2001Inventors: Hiroaki Shimada, Koji Yasojima, Shigeyuki Takeuchi
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Patent number: 6229180Abstract: A MOS type semiconductor apparatus is provided which includes a main MOS type semiconductor device, an internal control circuit connected between a control input terminal (G) and a control input port (g) of the main MOS type semiconductor device, and a protecting device connected between the control input terminal (G) and one of output terminals (S) of the apparatus, for protecting the semiconductor device or internal control circuit against overvoltage. The protecting device includes a first branch including a Zener diode (Z1p) consisting of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and a second branch including a Zener diode (Z21) formed in a surface layer of the semiconductor substrate, and a diode (Z3pr) that consists of a polysilicon layer deposited on an insulating film over the semiconductor substrate, and is connected in series with the Zener diode (Z21) in a reverse direction. The first and second branches are connected in parallel with each other.Type: GrantFiled: January 27, 1999Date of Patent: May 8, 2001Assignee: Fuji Electric Co., Ltd.Inventors: Kazuhiko Yoshida, Tatsuhiko Fujihira, Motoi Kudoh, Shoichi Furuhata, Shigeyuki Takeuchi
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Patent number: 6212755Abstract: A method for manufacturing an insert-resin-molded product prevents resin burrs from being generated. The method includes the steps of: preparing a resin-molding mold having a cavity having an inner wall including a recess formed therein; preparing a metallic member to be placed in the cavity of the resin-molding mold so as to be integrally molded with resin, the member having a metallic part to be fit into a recess of the resin-molding mold; placing the metallic member in the cavity of the resin-molding mold and fitting the metallic part of the metallic member into the recess of the resin-molding mold; and injecting resin into the cavity of the resin-molding mold to integrally insert-resin-mold with the metallic member.Type: GrantFiled: September 18, 1998Date of Patent: April 10, 2001Assignee: Murata Manufacturing Co., Ltd.Inventors: Hiroaki Shimada, Koji Yasojima, Shigeyuki Takeuchi
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Patent number: 5973359Abstract: A MOS type semiconductor device is provided which includes a series Zener diode array for overvoltage protection, which is provided between source regions and an electrode having substantially the same potential as a drain electrode, and a field insulating film on which the series Zener diode array is provided. The thickness T (.mu.m) of the field insulating film is determined as a function of the clamp voltage V.sub.CE (V) of the series Zener diode array, such that the thickness T is held in the range as represented by: T.gtoreq.2.0.times.10.sup.-3 .times.V.sub.CE. The width W.sub.1 (.mu.m) of a portion of a second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is provided, and the width W.sub.2 (.mu.m) of a portion of the second-conductivity-type isolation well that is close to the field insulating film on which the series Zener diode array is not provided, are determined as a function of the clamp voltage V.sub.Type: GrantFiled: November 12, 1998Date of Patent: October 26, 1999Assignee: Fuji Electric Co., Ltd.Inventors: Takashi Kobayashi, Tatsuhiko Fujihira, Shigeyuki Takeuchi, Yoshiki Kondo, Shoichi Furuhata
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Patent number: 5970964Abstract: A circuit is provided in which a voltage due to a minute current is applied to a gate terminal from a collector terminal when a collector voltage is higher than a gate voltage in an operation of current limitation. Thus, an increase in the collector voltage immediately after the operation of current limitation starts serves to boost the gate voltage. The boosted voltage suppress an abrupt increase in the collector voltage. When the collector voltage is reduced by oscillation, the action of boosting the gate voltage is lowered to suppress the reduction of the collector voltage.Type: GrantFiled: December 17, 1996Date of Patent: October 26, 1999Assignee: Fuji Electric Co., Ltd.Inventors: Shoichi Furuhata, Shigeyuki Takeuchi, Tatsuhiko Fujihira