Patents by Inventor Shih-An Cheng

Shih-An Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200028518
    Abstract: The present invention discloses an analog-to-digital converter (ADC) including an analog circuit, a first switch, a second switch, a first capacitor, and a second capacitor. The analog circuit has a first input terminal and a second input terminal and is configured to amplify and/or compare signals on the first input terminal and the second input terminal. One end of the first capacitor is coupled to the first input terminal, and the other end receives an input voltage via the first switch. One end of the second capacitor is coupled to the first input terminal, and the other end receives a reference voltage via the second switch.
    Type: Application
    Filed: April 15, 2019
    Publication date: January 23, 2020
    Inventors: YING-CHENG WU, SHIH-HSIUNG HUANG
  • Publication number: 20200027790
    Abstract: The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may be performed by forming a first conductive wire within a first dielectric structure formed on a first surface of a first substrate. A through-substrate-via (TSV) is formed to extend though the first substrate. A second conductive wire is formed within a second dielectric structure formed on a second surface of the first substrate opposing the first surface. The TSV electrically couples the first conductive wire and the second conductive wire. The first conductive wire, the second conductive wire, and the TSV define an inductor that wraps around an axis.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Publication number: 20200027789
    Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a first plurality of conductive interconnect layers arranged within a first inter-level dielectric (ILD) structure disposed on a first surface of a first substrate. A second plurality of conductive interconnect layers are arranged within a second ILD structure disposed on a first surface of a second substrate. The second substrate is separated from the first substrate by the first ILD structure. The first plurality of conductive interconnect layers and the second plurality of conductive interconnect layers define an inductor having one or more turns.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Shih-Han Huang, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao
  • Patent number: 10540313
    Abstract: Example implementations relate to computing devices with movable input/output (I/O) connectors. For example, a computing device may include a chassis of the computing device and an I/O connector to connect an I/O device to the computing device. The I/O connector may be movable about an axis relative to the chassis by at least 180 degrees such that the I/O connector is accessible from multiple sides of the chassis.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: January 21, 2020
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Shih Chuan Huang, Yu Cheng Wu, Chih Sheng Liao, Hsin Wen Hsu, Benjiman White, William E. Hertling, Mike Whitmarsh
  • Publication number: 20200015771
    Abstract: The invention provides a contrast carrier device with geometric calibration phantom on computed tomography, comprising: a front ring body having a front outer peripheral surface; the front outer peripheral surface is provided with a front correction bead; a loading table, wherein one end of the loading table is connected with the front ring body; a rear ring body is oppositely arranged at the other end of the front ring body connected to the loading table, wherein the rear ring body has an outer peripheral surface, the rear peripheral surface is provided with a rear correction bead; a virtual axis passes through the center of the front ring body and the center of the rear ring body, respectively, and the front correction bead and the rear correction bead.
    Type: Application
    Filed: February 5, 2019
    Publication date: January 16, 2020
    Inventors: Meng-Tse WU, Shih-Chun JIN, Jyh-Cheng CHEN
  • Patent number: 10534272
    Abstract: A method for exposing a wafer substrate includes forming a reticle having a device pattern. A relative orientation between the device pattern and a mask field of an exposure tool is determined based on mask field utilization. The reticle is loaded on the exposure tool. The wafer substrate is rotated based on an orientation of the device pattern. Radiation is projected through the reticle onto the rotated wafer substrate by the exposure tool, thereby imaging the device pattern onto the rotated wafer substrate.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
  • Patent number: 10535580
    Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Shih-Yi Syu
  • Patent number: 10529719
    Abstract: A semiconductor structure includes an active area in a substrate, a device isolation region surrounding the active area, first and second bit line structures on the substrate, a conductive diffusion region in the active area between the first and the second bit line structures, and a contact hole between the first and the second bit line structures. The contact hole partially exposes the conductive diffusion region. A buried plug layer is disposed in the contact hole and in direct contact with the conductive diffusion region. A storage node contact layer is disposed on the buried plug layer within the contact hole. The storage node contact layer has a downwardly protruding portion surrounded by the buried plug layer. The buried plug layer has a U-shaped cross-sectional profile.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: January 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Po-Han Wu, Li-Wei Feng, Shih-Han Hung, Fu-Che Lee, Chien-Cheng Tsai
  • Patent number: 10530483
    Abstract: Systems and methods described herein include methods and systems for controlling bias voltage provided to an optical modulating device. The optical modulating device is biased at a bias point that is different from a null point of the device such that an offset to the received optical power due to limited extinction ratio is reduced.
    Type: Grant
    Filed: February 6, 2019
    Date of Patent: January 7, 2020
    Assignee: INPHI CORPORATION
    Inventors: Shih Cheng Wang, Jinwoo Cho, Shu Hao Fan
  • Publication number: 20200006338
    Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei PENG, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Publication number: 20200003231
    Abstract: The disclosure provides a fan module and an electronic device. The fan module includes a hub and a plurality of blades. The blades are mounted around the hub, and each of the blades has a first end is connected to a periphery of the hub and a second end that is relatively away from the hub. A first axial direction distance in the axial direction is provided between a first point of the first end that is relative away from the top surface and the top surface. A second axial direction distance in the axial direction is provided between a second point of the first end that is near the top surface and the top surface. A ratio of the second axial direction distance to the first axial direction distance is 0.4 to 0.5.
    Type: Application
    Filed: April 30, 2019
    Publication date: January 2, 2020
    Applicant: Coretronic Corporation
    Inventors: Shih-Hang Lin, Chih-Cheng Chou
  • Publication number: 20200004914
    Abstract: An IC structure includes a first plurality of metal segments in a first metal layer, a second plurality of metal segments in a second metal layer overlying the first metal layer, and a third plurality of metal segments in a third metal layer overlying the second metal layer. The metal segments of the first and third pluralities of metal segments extend in a first direction, and the metal segments of the second plurality of metal segments extend in a second direction perpendicular to the first direction. A pitch of the third plurality of metal segments is smaller than a pitch of the second plurality of metal segments.
    Type: Application
    Filed: November 29, 2018
    Publication date: January 2, 2020
    Inventors: Shih-Wei PENG, Chih-Ming LAI, Charles Chew-Yuen YOUNG, Jiann-Tyng TZENG, Wei-Cheng LIN
  • Patent number: 10522542
    Abstract: Exemplary embodiments of an exemplary dual transmission gate and various exemplary integrated circuit layouts for the exemplary dual transmission gate are disclosed. These exemplary integrated circuit layouts represent double-height, also referred to as double rule, integrated circuit layouts. These double rule integrated circuit layouts include a first group of rows from among multiple rows of an electronic device design real estate and a second group of rows from among the multiple rows of the electronic device design real estate to accommodate a first metal layer of a semiconductor stack. The first group of rows can include a first pair of complementary metal-oxide-semiconductor field-effect (CMOS) transistors, such as a first p-type metal-oxide-semiconductor field-effect (PMOS) transistor and a first n-type metal-oxide-semiconductor field-effect (NMOS) transistor, and the second group of rows can include a second pair of CMOS transistors, such as a second PMOS transistor and a second NMOS transistor.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Peng, Hui-Zhong Zhuang, Jiann-Tyng Tzeng, Li-Chun Tien, Pin-Dai Sue, Wei-Cheng Lin
  • Publication number: 20190391701
    Abstract: An optical device is provided. The optical device includes a substrate including a plurality of pixel units, a dielectric layer disposed on the substrate, a patterned light-transmitting layer disposed on the dielectric layer and corresponding to the plurality of pixel units, and a plurality of continuous light-shielding layers disposed on the dielectric layer and located on both sides of the patterned light-transmitting layer. A method for fabricating an optical device is also provided.
    Type: Application
    Filed: June 25, 2018
    Publication date: December 26, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Cherng LIAO, Shih-Hao LIU, Wu-Hsi LU, Ming-Cheng LO, Chung-Ren LAO, Yun-Chou WEI, Yin CHEN, Hsin-Hui LEE, Hsueh-Jung LIN, Wen-Chih LU, Ting-Jung LU
  • Patent number: 10515955
    Abstract: Example embodiments relating to forming gate structures, e.g., for Fin Field Effect Transistors (FinFETs), are described. In an embodiment, a structure includes first and second device regions comprising first and second FinFETs, respectively, on a substrate. A distance between neighboring gate structures of the first FinFETs is less than a distance between neighboring gate structures of the second FinFETs. A gate structure of at least one of the first FinFETs has a first and second width at a level of and below, respectively, a top surface of a first fin. The first width is greater than the second width. A second gate structure of at least one of the second FinFETs has a third and fourth width at a level of and below, respectively a top surface of a second fin. A difference between the first and second widths is greater than a difference between the third and fourth widths.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Han Lin, Kuei-Yu Kao, Shih-Yao Lin, Ming-Ching Chang, Chao-Cheng Chen, Syun-Ming Jang
  • Patent number: 10516026
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a memory cell. The method may be performed by forming a select gate on a side of a sacrificial spacer that is disposed over an upper surface of a substrate. The select gate has a non-planar top surface. An inter-gate dielectric layer is formed on the select gate and a memory gate is formed on the inter-gate dielectric layer. The inter-gate dielectric layer extends under the memory gate and defines a recess between sidewalls of the memory gate and select gate. The recess is filled with a first dielectric material.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: December 24, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Ming Wu, Wei Cheng Wu, Shih-Chang Liu, Harry-Hak-Lay Chuang, Chia-Shiung Tsai
  • Patent number: 10515887
    Abstract: A semiconductor package structure is provided. The semiconductor package structure includes a first carrier substrate having a first surface and an opposing second surface. A second carrier substrate is stacked on the first carrier substrate and has a first surface and an opposing second surface that faces the first surface of the first carrier substrate. A semiconductor die is mounted on the first surface of the second carrier substrate. A heat spreader is disposed on the first surface of the first carrier substrate to cover and surround the second carrier substrate and the semiconductor die. A method for forming the semiconductor package structure is also provided.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: December 24, 2019
    Assignee: MediaTek Inc.
    Inventors: Shih-Yi Syu, Chia-Yu Jin, Che-Ya Chou, Wen-Sung Hsu, Nan-Cheng Chen
  • Patent number: 10510763
    Abstract: A nonvolatile memory embedded in an advanced logic circuit and a method forming the same are provided. In the nonvolatile memory, the word lines and erase gates have top surfaces lower than the top surfaces of the control gate. In addition, the word lines and the erase gates are surrounded by dielectric material before a self-aligned silicidation process is performed. Therefore, no metal silicide can be formed on the word lines and the erase gate to produce problems of short circuit and current leakage in a later chemical mechanical polishing process.
    Type: Grant
    Filed: May 26, 2017
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chang-Ming Wu, Wei-Cheng Wu, Yuan-Tai Tseng, Shih-Chang Liu, Chia-Shiung Tsai, Ru-Liang Lee, Harry Hak-Lay Chuang
  • Patent number: 10510729
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two integrated circuits are bonded together. A first opening is formed through one of the substrates. A multi-layer dielectric film is formed along sidewalls of the first opening. One or more etch processes form one or more spacer-shaped structures along sidewalls of the first opening. A second opening is formed extending from the first opening to pads in the integrated circuits. A dielectric liner is formed, and the opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Ting Tsai, Dun-Nian Yaung, Jen-Cheng Liu, U-Ting Chen, Shih Pei Chou
  • Patent number: D871812
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: January 7, 2020
    Assignees: King Slide Works Co., Ltd., King Slide Technology Co., Ltd.
    Inventors: Fang-Cheng Su, Ci-Bin Huang, Shih-Lung Huang, Shan-Yao Chen, Ching-Fu Chiu, Shu-Chen Lin