Patents by Inventor SHIH-AN HO

SHIH-AN HO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099086
    Abstract: A display may have an array of pixels. Display driver circuitry may supply data and control signals to the pixels. Each pixel may have seven transistors, a capacitor, and a light-emitting diode such as an organic light-emitting diode. The seven transistors may receive control signals using horizontal control lines. Each pixel may have first and second emission enable transistors that are coupled in series with a drive transistor and the light-emitting diode of that pixel. The first and second emission enable transistors may be coupled to a common control line or may be separately controlled so that on-bias stress can be effectively applied to the drive transistor. The display driver circuitry may have gate driver circuits that provide different gate line signals to different rows of pixels within the display. Different rows may also have different gate driver strengths and different supplemental gate line loading structures.
    Type: Application
    Filed: November 17, 2023
    Publication date: March 21, 2024
    Inventors: Cheng-Ho Yu, Chin-Wei Lin, Shyuan Yang, Ting-Kuo Chang, Tsung-Ting Tsai, Warren S. Rieutort-Louis, Shih-Chang Chang, Yu Cheng Chen, John Z. Zhong
  • Publication number: 20240048046
    Abstract: A boost power factor correction circuit includes: a switch and an inductor coupled to each other; a current sensing device generating a current sensing signal according to a current flowing through the switch; a temperature sensing device coupled to the inductor to generate a temperature sensing signal; and a conversion control circuit operating the switch. The conversion control circuit is an integrated circuit and includes: a shared pin coupled to the temperature sensing device and the current sensing device; and a current sensing circuit and a temperature sensing circuit which sense a multipurpose sensing signal through the shared pin. The multipurpose sensing signal is related to the current sensing signal when the switch is ON and related to the temperature sensing signal when the switch is OFF. The temperature sensing signal is related to an input voltage, an output voltage and an electrical parameter of the temperature sensing device.
    Type: Application
    Filed: July 9, 2023
    Publication date: February 8, 2024
    Inventors: Shih-Ho Hsu, Kun-Yu Lin, Wei-Hsu Chang
  • Publication number: 20240021230
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.
    Type: Application
    Filed: August 8, 2023
    Publication date: January 18, 2024
    Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
  • Publication number: 20230307268
    Abstract: A structure of transferring dies includes an oxide layer supporting feature, multiple dies, a bonding feature, a supporting wafer, and a spacer. The oxide layer supporting feature includes multiple repeating units. Each repeating unit has a die setting region and a peripheral region. The die setting region of one repeating unit is separated from the peripheral region of another adjacent repeating unit. The die is disposed on the die setting region and the bonding feature is disposed on the peripheral region of the oxide layer supporting feature. The supporting wafer is disposed under the oxide layer supporting feature and separated from the die and the bonding feature by a gap. The spacer is disposed between the bonding feature and the supporting wafer, and bonded to the bonding feature.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 28, 2023
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Yung-Hsiang Chen, Yun-Chou Wei, Ke-Fang Hsu, Ching-Yi Hsu, Yen-Shih Ho
  • Publication number: 20230278160
    Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yuan YANG, Huai-Tei YANG, Yu-Chen WEI, Szu-Cheng WANG, Li-Hsiang CHAO, Jen-Chieh LAI, Shih-Ho LIN
  • Publication number: 20230264317
    Abstract: A chemical mechanical polishing (CMP) apparatus is provided, including a polishing pad and a polishing head. The polishing pad has a polishing surface. The polishing head is configured to hold a wafer in contact with the polishing surface during the polishing process. The polishing head includes a retaining ring, at least one fluid channel, and a vacuum pump. The retaining ring is arranged along the periphery of the polishing head and configured to retain the wafer. The at least one fluid channel is provided inside the polishing head, wherein the retaining ring includes a bottom surface facing the polishing surface and a plurality of holes in fluid communication with the bottom surface and the at least one fluid channel. The vacuum pump is fluidly coupled to the at least one fluid channel.
    Type: Application
    Filed: April 28, 2023
    Publication date: August 24, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen WEI, Jheng-Si SU, Shih-Ho LIN, Jen-Chieh LAI, Chun-Chieh CHAN
  • Publication number: 20230268825
    Abstract: A power supply system includes a power factor correction converter circuit and an isolated power converter circuit, wherein the power factor correction converter circuit corrects the power factor of a rectified power to generate a first output power, and the isolated power converter circuit converts the first output power to generate a second output power. The isolated power converter circuit includes a transformer, and the transformer includes a primary winding, a secondary winding, and an auxiliary winding. The auxiliary winding generates an auxiliary voltage which is related to the second output power. When the auxiliary voltage is lower than a disabled threshold, indicating that the voltage of the second output power is lower than a threshold, the power factor correction converter circuit provides a bypassing connection from the rectified power to the first output power and stops correcting the power factor of the rectified power.
    Type: Application
    Filed: January 19, 2023
    Publication date: August 24, 2023
    Inventors: Wei-Hsu Chang, Ta-Yung Yang, Shih-Ho Hsu, Mao-Hui Kuo
  • Patent number: 11697993
    Abstract: A rotary engine is provided, including: a stator assembly, including an intake stator including an annular intake groove and an exhaust stator including an annular exhaust groove which define a track therebetween; a rotor, rotatably disposed between the intake and exhaust stators, including cylinders each being covered by one of the cylinder head and cylinder heads each including an intake port and an exhaust port, the intake and exhaust ports being connected to the annular intake and exhaust grooves, respectively; a shaft, inserted axially in the stator assembly and the rotor; valve mechanisms, posited on the cylinder heads respectively and each including an intake valve and an exhaust valve; pistons, received in the cylinders respectively and each including a piston rod which is movable along the track; and spark plugs, posited on the cylinder heads and exposed to interiors of the cylinders, respectively.
    Type: Grant
    Filed: December 28, 2022
    Date of Patent: July 11, 2023
    Inventors: Shih-Ho Chang, Han-Chih Chang, Hsin-Yu Chang
  • Patent number: 11685015
    Abstract: A method of using a polishing system includes securing a wafer in a carrier head, the carrier head including a housing enclosing the wafer, in which the housing includes a retainer ring recess and a retainer ring positioned in the retainer ring recess, the retainer ring surrounding the wafer, in which the retainer ring includes a main body portion and a bottom portion connected to the main body portion, and a bottom surface of the bottom portion includes at least one first engraved region and a first non-engraved region adjacent to the first engraved region; pressing the wafer against a polishing pad; and moving the carrier head or the polishing pad relative to the other.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 27, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yuan Yang, Huai-Tei Yang, Yu-Chen Wei, Szu-Cheng Wang, Li-Hsiang Chao, Jen-Chieh Lai, Shih-Ho Lin
  • Patent number: 11673223
    Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: June 13, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
  • Publication number: 20230073729
    Abstract: A method and an apparatus for compensating image segmentation lines are provided. In the method, image segmentation is applied to a medical image captured by using a segmentation model to obtain a segmentation image including at least one segmentation line between multiple layers in the medical image. Convolution computation is then performed on the segmentation image by using a kernel of a trained classification model to predict a location of a next pixel connected to a current pixel in the respective segmentation line within the segmentation image, in which the pixel to be predicted is limited to a neighboring pixel of the current pixel in a prediction direction. The predicted pixels are connected to form a compensated segmentation line for each segmentation line.
    Type: Application
    Filed: October 20, 2021
    Publication date: March 9, 2023
    Applicant: Acer Medical Inc.
    Inventors: Shih-Ho Huang, Ming-Tzuo Yin
  • Patent number: 11536554
    Abstract: A localization and attitude estimation method using magnetic fields includes the following steps. First, in three-dimensional coordinates, at least three magnetic landmarks arbitrarily disposed around a moving carrier are selected, wherein any two of the at least three magnetic landmarks have different magnetic directions. One set of at least five tri-axes magnetic sensors is used to sense the magnetic fields of the at least three magnetic landmarks. Three magnetic components on three axes of a current position of each of the tri-axes magnetic sensors are respectively generated by a demagnetization method. Five non-linear magnetic equations are solved to obtain position information and magnetic moment information of the at least three magnetic landmarks in the three-dimensional coordinates. Position vectors and attitude vectors of the set of at least five tri-axes magnetic sensors in a three-dimensional space are estimated based on tri-axes magnetic moment vectors of the magnetic landmarks.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: December 27, 2022
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Sheng-Wen Luo, Shih-Ho Hsieh, Jwu-Sheng Hu
  • Patent number: 11476293
    Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: October 18, 2022
    Assignee: XINTEC INC.
    Inventors: Yen-Shih Ho, Tsang-Yu Liu, Po-Han Lee
  • Patent number: 11455498
    Abstract: A model training method and an electronic device are provided. The method includes the following steps: establishing a brain age prediction model according to a training set; adjusting a parameter in the brain age prediction model according to a validation set; inputting a test set into the brain age prediction model with the adjusted parameter to obtain a plurality of first predicted brain ages; determining whether the first predicted brain ages satisfy a first specific condition; and completing training of the brain age prediction model when the first predicted brain ages satisfy the first specific condition.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: September 27, 2022
    Assignees: Acer Incorporated, National Yang-Ming University
    Inventors: Cheng-Tien Hsieh, Chun-Hsien Yu, Shih-Ho Huang, Meng-Che Cheng, Kun-Hsien Chou, Ching-Po Lin, Liang-Kung Chen
  • Publication number: 20220229567
    Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.
    Type: Application
    Filed: February 10, 2022
    Publication date: July 21, 2022
    Inventors: Shih-ho WU, Christopher HAYWOOD
  • Publication number: 20220219285
    Abstract: A chemical mechanical polishing method is provided, including polishing a batch of wafers in sequence on a polishing surface of a polishing pad; conditioning the polishing surface with a pad conditioner, wherein the pad conditioner is operable to apply downward force according to a predetermined downward force stored in a controller to condition the polishing surface; measuring the downward force applied by the pad conditioner with a measurement tool when the pad conditioner is at a home position and after conditioning the polishing surface; comparing the downward force measured by the measurement tool and the predetermined downward force with the controller to determine whether a difference between the downward force measured by the measurement tool and the predetermined downward force exceeds a range of acceptable values; and calibrating the downward force applied by the pad conditioner with the controller when the difference exceeds the range of acceptable values.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen WEI, Jheng-Si SU, Shih-Ho LIN, Jen-Chieh LAI, Chun-Chieh CHAN
  • Publication number: 20220115243
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first layer over a substrate. The method includes forming a stop layer over the first layer. The method includes forming a second layer over the stop layer. The second layer is in direct contact with the stop layer. The method includes partially removing the second layer. The method includes performing an etching process to partially remove the stop layer and an upper portion of the first layer, wherein protrusion structures are formed over a lower portion of the first layer after the etching process, and the protrusion structures include the stop layer and the upper portion of the first layer remaining after the etching process. The method includes removing the protrusion structures.
    Type: Application
    Filed: December 20, 2021
    Publication date: April 14, 2022
    Inventors: Yu-Chen WEI, Chun-Chieh CHAN, Chun-Jui CHU, Jen-Chieh LAI, Shih-Ho LIN
  • Patent number: 11292101
    Abstract: A chemical mechanical polishing apparatus is provided. The chemical mechanical polishing apparatus includes a polishing pad, a pad conditioner, a measurement tool, and a controller. The polishing pad is provided in a processing chamber for polishing a wafer placed on the polishing surface of the polishing pad. The pad conditioner is configured to condition the polishing surface. The measurement tool is provided in the processing chamber and configured to measure the downward force of the pad conditioner. The controller is coupled to the pad conditioner and the measurement tool, and is configured to adjust the downward force of the pad conditioner in response to an input from the measurement tool.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: April 5, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Chen Wei, Jheng-Si Su, Shih-Ho Lin, Jen-Chieh Lai, Chun-Chieh Chan
  • Patent number: 11249658
    Abstract: The present invention is directed to computer storage systems and methods thereof. In an embodiment, a memory system comprises a controller module, a nonvolatile memory, and a volatile memory. The controller module operates according to a command and operation table. The command and operation table can be updated to change the way controller module operates. When the command and operation table is updated, the updated table is stored at a predefined location of the nonvolatile memory. There are other embodiments as well.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: February 15, 2022
    Assignee: Rambus, Inc.
    Inventors: Shih-ho Wu, Christopher Haywood
  • Patent number: 11251063
    Abstract: A transporter for transporting an article used in semiconductor fabrication is provided. The transporter includes a robotic arm. The transporter further includes two platens connected to the robotic arm. Each of the two platens an inner surface facing the other, and a number of gas holes are formed on each of the inner surfaces of the two platens. The transporter also includes a gas supplier placed in communication with the gas holes. The gas supplier is used to control the flow of gas through the gas holes.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: February 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jheng-Si Su, Yu-Chen Wei, Chih-Yuan Yang, Shih-Ho Lin, Jen-Chieh Lai