Patents by Inventor Shih-An Huang
Shih-An Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250072071Abstract: A transistor structure includes a substrate, a first well region, a second well region, a gate structure, a drift region, a first doped region, a second doped region, and a first isolation structure. The first well region and the second well region are located in the substrate and adjacent to each other. The gate structure is located on the substrate. The drift region is located in the second well region on one side of the gate structure. The first doped region and the second doped region are located in the substrate on two sides of the gate structure. The first doped region is located in the first well region. The second doped region is located in the drift region. The first isolation structure is located in the substrate between the gate structure and the second doped region. The first well region has a first portion lower than a bottom surface of the drift region. The second well region has a second portion lower than the bottom surface of the drift region.Type: ApplicationFiled: September 15, 2023Publication date: February 27, 2025Applicant: United Microelectronics Corp.Inventors: Chih Wen Huang, Shih An Huang
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Publication number: 20240313074Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wen Huang, Shih-An Huang
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Patent number: 12021129Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.Type: GrantFiled: September 15, 2022Date of Patent: June 25, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wen Huang, Shih-An Huang
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Publication number: 20240145564Abstract: The invention provides a semiconductor structure, which comprises a substrate, a gate dielectric layer on the substrate, wherein the gate dielectric layer comprises two sidewall portions and a horizontal portion between the two sidewall portions, wherein a height of the horizontal portion is lower than that of the two sidewall portions, and the horizontal portion and the two sidewall portions are perpendicular to each other, and a gate conductive layer on the horizontal portion of the gate dielectric layer.Type: ApplicationFiled: November 25, 2022Publication date: May 2, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tzu-I Tsai, Shih-An Huang
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Publication number: 20230014945Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.Type: ApplicationFiled: September 15, 2022Publication date: January 19, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wen Huang, Shih-An Huang
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Patent number: 11482605Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.Type: GrantFiled: December 20, 2020Date of Patent: October 25, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wen Huang, Shih-An Huang
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Publication number: 20220149171Abstract: A work function metal gate device includes a gate, a drift region, a source, a drain and a first isolation structure. The gate includes a convex stair-shaped work function metal stack or a concave stair-shaped work function metal stack disposed on a substrate. The drift region is disposed in the substrate below a part of the gate. The source is located in the substrate and the drain is located in the drift region beside the gate. The first isolation structure is disposed in the drift region between the gate and the drain.Type: ApplicationFiled: December 20, 2020Publication date: May 12, 2022Inventors: Chih-Wen Huang, Shih-An Huang
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Patent number: 9502260Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.Type: GrantFiled: January 19, 2015Date of Patent: November 22, 2016Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-An Huang, Kun-Hsien Lee
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Publication number: 20160189970Abstract: The present invention provides a method for forming a semiconductor structure, including: firstly, providing a substrate, a fin structure being disposed on the substrate, a gate structure crossing over the fin structure, and a first hard mask being disposed on the top surface of the gate structure. Next, a dielectric layer is formed, covering the substrate, the fin structure and the gate structure. Afterwards, a second hard mask is formed on the top surface of the first hard mask, where the width of the second hard mask is larger than the width of the first hard mask, a bottom surface of the second hard mask and a top surface of the first hard mask are on the same level. An etching process is then performed to remove parts of the dielectric and parts of the fin structure.Type: ApplicationFiled: January 19, 2015Publication date: June 30, 2016Inventors: Shih-An Huang, Kun-Hsien Lee