Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.

Abstract: A method for atomic layer etching a metal containing layer is provided. At least a region of a surface of the metal containing layer is modified to form a modified metal containing region by exposing a surface of the metal containing layer to a modification gas, wherein adjacent to the modified metal containing region remains an unmodified metal containing region. The modified metal containing region is selectively removed with respect to the unmodified metal containing region by exposing the surface of the metal containing layer to an inert bombardment plasma generated from an inert gas.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism includes a movable part, a fixed part, and a driving assembly. The movable part connects an optical element. The movable part is movable relative to the fixed part. The driving assembly drives the optical element to move relative to the fixed part.

Abstract: A lateral-bipolar junction transistor (BJT) including a semiconductor substrate, an insulator region disposed on the semiconductor substrate, and a well region comprising a well semiconductor of a first conductivity type disposed over the insulator region. An emitter region of a second conductivity type is disposed in the well region, and at least one collector region of a second conductivity type is disposed in the well region. A T shaped, Pi shaped or H shaped gate and gate oxide layer includes a gate portion extending between the emitter region and one or more collector regions, and a base is disposed underneath the gate portion. In other embodiments, a metal oxide semiconductor (MOS) transistor-based circuit similarly employs a compact Pi or H shaped gate and gate oxide layer.

Abstract: An optical element driving mechanism is provided. The optical element driving mechanism is for driving an optical element. The optical element includes a movable part, a fixed part, and a driving assembly. The movable part may move relative to the fixed part. The driving assembly drives the movable part to move.

Abstract: A heat pipe comprises a flat tube and a wick structure. The flat tube includes a hollow chamber and has a front and a rear sealed ends along an axial direction. The wick structure is disposed in the hollow chamber and extended along the axial direction of the flat tube. The wick structure is divided into a front, a middle and a rear sections sequentially along the axial direction. The front section is near the front sealed end, the rear section is near the rear sealed end. The front, middle and rear sections have a maximum length parallel to the width direction, respectively. The maximum length of the front section is greater than that of the middle section, and the maximum length of the middle section is greater than that of the rear section.

Abstract: Methods of manufacturing electronic devices, such as transistors (negative metal-oxide-semiconductor (NMOS) transistors (e.g., an N-metal stack) and positive metal-oxide-semiconductor (PMOS) transistors (e.g., a P-metal stack)) are described. Embodiments of the disclosure are directed to methods of improving PMOS transistor performance by inhibiting N-metal layer growth. The present disclosure provides two types of processes to reduce or inhibit N-metal layer growth. The disclosure provides methods which include forming a self-assembled monolayer (SAM) on the metal surface (e.g., titanium nitride (TiN)) of the PMOS, and methods which include forming a silicon-containing layer such as silicon oxide (SiOx) on the TiN surface. These two types of processes significantly reduce or inhibit the subsequent growth of an N-metal layer, such as titanium aluminum carbide (TiAlC), on the TiN surface of the PMOS.

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: detecting a status of a rewritable non-volatile memory module; and determining whether to perform a data refresh operation on the rewritable non-volatile memory module according to a first condition and a second condition. The first condition is related to a first physical unit in the rewritable non-volatile memory module. The second condition is related to a plurality of second physical units in the rewritable non-volatile memory module. The data refresh operation is configured to update data in the rewritable non-volatile memory module to reduce a bit error rate of the data.

Abstract: A display may include an array of pixels such as light-emitting diode pixels. The pixels may include multiple circuitry decks that each include one or more circuit components such as transistors, capacitors, and/or resistors. The circuitry decks may be vertically stacked. Each circuitry deck may include a planarization layer formed from a siloxane material that conforms to underlying components and provides a planar upper surface. In this way, circuitry components may be vertically stacked to mitigate the size of each pixel footprint. The circuitry components may include capacitors that include both a high-k dielectric layer and a low-k dielectric layer. The display pixel may include a via with a width of less than 1 micron.

Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.

Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.

Abstract: A head-mounted eye tracking system including a light-transmitting substrate, an eye tracker, and a signal processor is provided. The eye tracker is configured to sense eyeballs of a wearer. The eye tracker includes a plurality of light-emitting devices and a plurality of sensing devices. The plurality of light-emitting devices are configured to emit a tracking beam. The plurality of sensing devices are configured to receive the tracking beam reflected by the eyeballs of the wearer. The signal processor is electrically connected to the eye tracker. The plurality of sensing devices are embedded in grooves within the light-transmitting substrate.

Abstract: A cavity-backed slot antenna system provided in this disclosure is installed in a housing of an electronic device and includes a metal cavity, a supporting element, an antenna device, a conductive post, and a coupling metal part. The metal cavity is in the housing and includes an opening and a closed surface opposite to each other. A slot is on the closed surface. The supporting element is in the metal cavity. The antenna device is in the metal cavity and on the supporting element, to expose one side surface of the antenna device. The antenna device includes a feed source. The conductive post penetrates the antenna device and connects to the metal cavity. The coupling metal part is in the housing and close to the opening of the metal cavity, so that the coupling metal part is close to and corresponds to the feed source of the antenna device.

Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.

Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.

Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.

Abstract: A device includes a first die, an interconnect structure, a RDL layer, a guard structure and an underfill layer. The interconnect structure is electrically connected to the first die. The RDL layer is disposed in a dielectric layer. The guard structure is disposed in the dielectric layer to define a connector region, wherein the guard structure and the interconnect structure are disposed on opposite sides of the die. The underfill layer surrounds the interconnect structure, the first die and the guard structure, wherein the underfill layer is kept outside of the connector region by the guard structure.

Abstract: Disclosed is an image display device including a display device, an optical modulation element, and a modulation device. When the modulation device is in a first state, the display device projects a first image at a first imaging position through the optical modulation element. When the modulation device is in a second state, the display device projects a second image at a second imaging position through the optical modulation element. A minimum distance from the first imaging position to the optical modulation element is different from a minimum distance from the second imaging position to the optical modulation element.

Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as finFETs, GAAs, and the like, without creating a seam. The methods include selective deposition processes using blocking compounds in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.