Patents by Inventor Shih-An Lin

Shih-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12242788
    Abstract: A method includes providing a placing layout of the integrated circuit; generating a routed layout including a layout region with a systematic design rule check (DRC) violation; and performing a loop when the DRC the systematic DRC violation exists. The loop includes: generating an adjusted routing layout of the integrated circuit by adjusting the layout region with the systematic DRC violation according to a target placement recipe; extracting features of the placing layout to obtain extracted data; extracting features of the layout region with the systematic DRC violation to obtain extracted routing data; generating a plurality of aggregated-cluster models based upon the extracted data and the extracted routing data; selecting a target aggregated-cluster model from the plurality of aggregated-cluster models by comparing the extracted data to the plurality of aggregated-cluster models; and selecting the target placement recipe from a plurality of placement recipes to generate the adjusted routing layout.
    Type: Grant
    Filed: May 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shih-Yao Lin, Yi-Lin Chuang, Yin-An Chen, Shih Feng Hong
  • Patent number: 12242313
    Abstract: A system determines a current state of an information handling system, and receives a sensor output signal. The system determines whether a status change of the sensor output signal relates to an expected state based on the current state and a previous state of the information handling system, and determines whether the sensor output signal is triggered by an external magnet. If the status change of the sensor output signal relates to the expected state and the sensor output signal is not triggered by the external magnet, then the system transitions the information handling system from the current state to the expected state.
    Type: Grant
    Filed: September 28, 2023
    Date of Patent: March 4, 2025
    Assignee: Dell Products L.P.
    Inventors: Chen Hsin Chang, Wan Shih Chien, Yi Min Lin
  • Publication number: 20250067976
    Abstract: A head-mounted eye tracking system including a light-transmitting substrate, an eye tracker, and a signal processor is provided. The eye tracker is configured to sense eyeballs of a wearer. The eye tracker includes a plurality of light-emitting devices and a plurality of sensing devices. The plurality of light-emitting devices are configured to emit a tracking beam. The plurality of sensing devices are configured to receive the tracking beam reflected by the eyeballs of the wearer. The signal processor is electrically connected to the eye tracker. The plurality of sensing devices are embedded in grooves within the light-transmitting substrate.
    Type: Application
    Filed: November 8, 2024
    Publication date: February 27, 2025
    Applicant: Industrial Technology Research Institute
    Inventors: Han-Kuei Fu, Meng-Han Lin, Hsu-Shih Huang, Ming-Hsien Wu, Chia-Hsin Chao, Wei-Hung Kuo
  • Patent number: 12237400
    Abstract: A method of forming a semiconductor device includes: forming a semiconductor structure having source/drain regions, a fin disposed between the source/drain regions, and a dummy gate disposed on the fin and surrounded by a spacer; removing the dummy gate to form a gate trench which is defined by a trench-defining wall; forming a gate dielectric layer on the trench-defining wall; forming a work function structure on the gate dielectric layer; forming a resist layer to fill the gate trench; removing a top portion of the resist layer; removing the work function structure exposed from the resist layer using a wet chemical etchant; removing the resist layer; and forming a conductive gate in the gate trench.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chieh-Wei Chen, Jian-Jou Lian, Tzu-Ang Chiang, Po-Yuan Wang, Yu-Shih Wang, Chun-Neng Lin, Ming-Hsi Yeh
  • Patent number: 12237577
    Abstract: A cavity-backed slot antenna system provided in this disclosure is installed in a housing of an electronic device and includes a metal cavity, a supporting element, an antenna device, a conductive post, and a coupling metal part. The metal cavity is in the housing and includes an opening and a closed surface opposite to each other. A slot is on the closed surface. The supporting element is in the metal cavity. The antenna device is in the metal cavity and on the supporting element, to expose one side surface of the antenna device. The antenna device includes a feed source. The conductive post penetrates the antenna device and connects to the metal cavity. The coupling metal part is in the housing and close to the opening of the metal cavity, so that the coupling metal part is close to and corresponds to the feed source of the antenna device.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: February 25, 2025
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Shih-Hsun Chang, Wei-Lin Tsai, Zhi-Zeng Cheng, You-Fu Cheng, Tsung-Hsun Hsieh
  • Publication number: 20250062136
    Abstract: A method includes bonding a device die onto a package component. The device die includes a semiconductor substrate, and a through-via extending into the semiconductor substrate. The method further includes depositing a dielectric liner lining sidewalls of the device die, depositing a dielectric layer on the dielectric liner, and planarizing the dielectric layer and the device die. Remaining portions of the dielectric liner and the dielectric layer form a gap-filling region, and a top end of the through-via is revealed. An implantation process is performed to introduce a stress modulation dopant into at least one of the dielectric liner and the dielectric layer. A redistribution line is formed over and electrically connecting to the through-via.
    Type: Application
    Filed: November 20, 2023
    Publication date: February 20, 2025
    Inventors: Ming-Tsu Chung, Yung-Chi Lin, Yan-Zuo Tsai, Yang-Chih Hsueh, Ming-Shih Yeh
  • Publication number: 20250056872
    Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a substrate, an active region on the substrate, and a gate structure, a source conductor, and a drain conductor disposed on the active region. The semiconductor device further comprises a first type doped region of the active region below the gate structure and a second type doped region of the active region adjacent to the first type doped region, and the first type doped region is different from the second type doped region. The second type doped region is configured to function as a resistor.
    Type: Application
    Filed: August 11, 2023
    Publication date: February 13, 2025
    Inventors: WAN-LIN TSAI, KAI-QIANG WEN, I-SHENG CHEN, YI-JING LI, SHIH-CHUN FU, CLEMENT HSINGJEN WANN
  • Publication number: 20250054894
    Abstract: A device includes a first die, an interconnect structure, a RDL layer, a guard structure and an underfill layer. The interconnect structure is electrically connected to the first die. The RDL layer is disposed in a dielectric layer. The guard structure is disposed in the dielectric layer to define a connector region, wherein the guard structure and the interconnect structure are disposed on opposite sides of the die. The underfill layer surrounds the interconnect structure, the first die and the guard structure, wherein the underfill layer is kept outside of the connector region by the guard structure.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hua-Wei Tseng, Yueh-Ting Lin, Shao-Yun Chen, Li-Hsien Huang, An-Jhih Su, Ming-Shih Yeh, Der-Chyang Yeh
  • Publication number: 20250046600
    Abstract: One or more embodiments of the disclosure are directed to methods of forming structures that are useful for FEOL and BEOL processes. Embodiments of the present disclosure advantageously provide methods of depositing titanium nitride (TiN) in high aspect ratio (AR) structures with small dimensions. Some embodiments advantageously provide seam-free high-quality TiN films to fill high AR trenches with small dimensions. Embodiments of the present disclosure advantageously provide methods of filling 3D structures, such as finFETs, GAAs, and the like, without creating a seam. The methods include selective deposition processes using blocking compounds in order to provide seam-free TiN gapfill in 3D structures, such as GAA devices.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Muthukumar Kaliappan, Zhebo Chen, Michael Haverty, Yongjing Lin, Shih Chung Chen, Gang Shen, Alexander Jansen, Janardhan Devrajan
  • Publication number: 20250044612
    Abstract: Disclosed is an image display device including a display device, an optical modulation element, and a modulation device. When the modulation device is in a first state, the display device projects a first image at a first imaging position through the optical modulation element. When the modulation device is in a second state, the display device projects a second image at a second imaging position through the optical modulation element. A minimum distance from the first imaging position to the optical modulation element is different from a minimum distance from the second imaging position to the optical modulation element.
    Type: Application
    Filed: July 7, 2024
    Publication date: February 6, 2025
    Applicant: InnoLux Corporation
    Inventors: En-Jie CHEN, Yu-Shih TSOU, Yu-Wei TU, Chih-Lung LIN
  • Patent number: 12216980
    Abstract: A method includes the following operations: identifying a layer of a first layout based on a first violation generated on the layer; generating a metal density value associated with the layer; when the metal density value is larger than or equal to a preset value, classifying the first violation into a first class corresponding to routing congestions of the first layout; when the first violation is classified into the first class, assigning, to the first violation, a first operation of a plurality of first pre-stored operations corresponding to the first class; and performing the first operation to the first layout to generate a second layout.
    Type: Grant
    Filed: July 27, 2022
    Date of Patent: February 4, 2025
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., TSMC NANJING COMPANY LIMITED
    Inventors: Yi-Lin Chuang, Song Liu, Pei-Pei Chen, Heng-Yi Lin, Shih-Yao Lin, Chin-Hsien Wang
  • Patent number: 12216326
    Abstract: An optical member driving mechanism for connecting an optical member is provided, including a fixed portion and a first adhesive member. The fixed portion includes a first member and a second member, wherein the first member is fixedly connected to the second member via the first adhesive member.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: February 4, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Hsiang-Chin Lin, Shou-Jen Liu, Guan-Bo Wang, Kai-Po Fan, Chan-Jung Hsu, Shao-Chung Chang, Shih-Wei Hung, Ming-Chun Hsieh, Wei-Pin Chin, Sheng-Zong Chen, Yu-Huai Liao, Sin-Hong Lin, Wei-Jhe Shen, Tzu-Yu Chang, Kun-Shih Lin, Che-Hsiang Chiu, Sin-Jhong Song
  • Publication number: 20250037858
    Abstract: The present invention disclose a medical image-based system for predicting lesion classification and a method thereof. The system comprises a feature data extracting module for providing a raw feature data based on a medical image, and a predicting module for outputting a predicted class and a risk index according to the raw feature data. The predicting module comprises a classification unit for generating the predicted class and a prediction score corresponding thereto according to the raw feature data, and a risk evaluation unit for generating the risk index according to the prediction score. The system provides medical personnels a reference score and a risk index to determine progression of a certain disease.
    Type: Application
    Filed: February 1, 2024
    Publication date: January 30, 2025
    Inventors: YI-SHAN TSAI, YU-HSUAN LAI, CHENG-SHIH LAI, CHAO-YUN CHEN, MENG-JHEN WU, YI-CHUAN LIN, YI-TING CHIANG, PENG-HAO FANG, PO-TSUN KUO, YI-CHIH CHIU
  • Publication number: 20250031929
    Abstract: A cleaning system and a cleaning method are provided. The cleaning system includes a main body, an air suctioning device, a light source, an optical sensor, a memory and a processing unit. The air suctioning device includes an air flow passage and a fan-motor assembly that is disposed in the air flow passage and generates a suction force to suction outside air through the air flow passage. The light source emit light to the air flow passage. The optical sensor captures a plurality of successive image frames from the air flow passage. The processing unit is configured to: obtain first and second image frames from the successive image frames; compare the first image frame with the second image frame to identify dust particles; obtain a particle feature of the dust particles; and determine a current cleanness condition according to the particle feature.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: SHIH-FENG CHEN, HAN-LIN CHIANG, NING SHYU
  • Patent number: 12210208
    Abstract: A driving mechanism is provided for moving an optical element, including a fixed module, a movable module holding the optical element, a driving assembly for driving the movable module to move relative to the fixed module, a position-sensing element, and a 3D circuit. The fixed module has a base, and the position-sensing element is disposed on the base to detect the movement of the movable module relative to the fixed module. The 3D circuit is embedded in the base and electrically connected to the position-sensing element.
    Type: Grant
    Filed: June 21, 2019
    Date of Patent: January 28, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Shao-Chung Chang, Fu-Yuan Wu, Yu-Huai Liao, Shou-Jen Liu, Kun-Shih Lin, Chien-Lun Huang, Shih-Wei Hung
  • Patent number: 12211752
    Abstract: A method for forming a semiconductor device includes patterning a substrate to form a strip including a first semiconductor material, forming an isolation region along a sidewall of the strip, an upper portion of the strip extending above the isolation region, forming a dummy structure along sidewalls and a top surface of the upper portion of the strip, performing a first etching process on an exposed portion of the upper portion of the strip to form a first recess, the exposed portion of the strip being exposed by the dummy structure, after performing the first etching process, reshaping the first recess to have a V-shaped bottom surface using a second etching process, wherein the second etching process is selective to first crystalline planes having a first orientation relative to second crystalline planes having a second orientation, and epitaxially growing a source/drain region in the reshaped first recess.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Lin, Kun-Yu Lee, Shahaji B. More, Cheng-Han Lee, Shih-Chieh Chang
  • Patent number: 12211782
    Abstract: A package comprises at least one first device die, and a redistribution line (RDL) structure having the at least one first device die bonded thereto. The RDL structure comprises a plurality of dielectric layers, and a plurality of RDLs formed through the plurality of dielectric layers. A trench is defined proximate to axial edges of the RDL structure through each of the plurality of dielectric layers. The trench prevents damage to portions of the RDL structure located axially inwards of the trench.
    Type: Grant
    Filed: August 10, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yueh-Ting Lin, Hua-Wei Tseng, Ming Shih Yeh, Der-Chyang Yeh
  • Publication number: 20250029949
    Abstract: A wafer stacking process is provided in the present invention, including steps of forming a silicon oxide layer on a sacrificial carrier, bonding the silicon oxide layer with a dielectric layer on a front side of a silicon substrate, performing a thinning process on the back side of the silicon substrate to expose TSVs therewithin, bonding the back side of the silicon substrate with another silicon substrate, repeating the thinning process and the process of bonding another silicon substrate above so as to form a wafer stacking structure, and performing a removing process to completely remove the sacrificial carrier.
    Type: Application
    Filed: November 1, 2023
    Publication date: January 23, 2025
    Applicant: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Chih-Feng Sung, Chih-Hao Chuang, Chun-Lin Lu, Shih-Ping Lee, Li-Han Chiu, Yi-Kai Wu
  • Publication number: 20250028143
    Abstract: A driving mechanism for moving an optical element is provided, including a fixed part, a movable part, a driving assembly, and a first guiding member connected between the fixed part and the movable part. The optical element is disposed on the movable part, and the driving assembly drives the movable part to move relative to the fixed part. The first guiding member is configured for guiding the movable part to move relative to the fixed part.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 23, 2025
    Inventors: Po-Xiang ZHUANG, Yi-Fan LEE, Chao-Yuan CHANG, Wei-Jhe SHEN, Sin-Jhong SONG, Kun-Shih LIN, Yi-Ho CHEN, Chao-Chang HU
  • Patent number: 12205886
    Abstract: The present disclosure provides a semiconductor device that includes a substrate, a first dielectric layer over the substrate, and an interconnect layer over the first dielectric layer. The interconnect layer includes a plurality of metal lines and a second dielectric layer filling space between the plurality of metal lines. The plurality of metal lines includes a first metal line having a first bulk metal layer of a noble metal and a second metal line having a second bulk metal layer of a non-noble metal.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Kang Fu, Ming-Han Lee, Shau-Lin Shue