Abstract: A dynamic current correlating circuit is disclosed. The current correlating circuit includes a reset circuit, a first current generating circuit and a second current generating circuit. The reset circuit executes a discharging procedure during a first time interval and executes a charging procedure during a second time interval. The first current generating circuit is electrically connected to the reset circuit. The first current generating circuit generates a first sub-current and a second sub-current during a third time interval according to a first input voltage and a second input voltage and generates a first current after the third time interval. The second current generating circuit is electrically connected to the reset circuit. The second current generating circuit generates a second current according to the first input voltage and the second input voltage after the third time interval.

Abstract: A dynamic current correlating circuit is disclosed. The current correlating circuit includes a reset circuit, a first current generating circuit and a second current generating circuit. The reset circuit executes a discharging procedure during a first time interval and executes a charging procedure during a second time interval. The first current generating circuit is electrically connected to the reset circuit. The first current generating circuit generates a first sub-current and a second sub-current during a third time interval according to a first input voltage and a second input voltage and generates a first current after the third time interval. The second current generating circuit is electrically connected to the reset circuit. The second current generating circuit generates a second current according to the first input voltage and the second input voltage after the third time interval.

Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

Abstract: A frequency calibration method for calibrating an output frequency of a voltage-controlled oscillator is provided. The voltage-controlled oscillator includes a first capacitor bank, a second capacitor bank, and a third capacitor bank. The first capacitor bank and the third capacitor bank are initially disabled and the second capacitor bank is initially enabled. The method includes, when the initial output frequency is lower than a reference frequency, adjusting the capacitance of the second capacitor bank until the calibrated output frequency is greater than the reference frequency, and when the initial output frequency is greater than the reference frequency, enabling the first capacitor bank and gradually increasing the capacitance of the first capacitor bank until the calibrated output frequency is lower than the reference frequency.

Abstract: A frequency calibration method for calibrating an output frequency of a voltage-controlled oscillator is provided. The voltage-controlled oscillator includes a first capacitor bank, a second capacitor bank, and a third capacitor bank. The first capacitor bank and the third capacitor bank are initially disabled and the second capacitor bank is initially enabled. The method includes, when the initial output frequency is lower than a reference frequency, adjusting the capacitance of the second capacitor bank until the calibrated output frequency is greater than the reference frequency, and when the initial output frequency is greater than the reference frequency, enabling the first capacitor bank and gradually increasing the capacitance of the first capacitor bank until the calibrated output frequency is lower than the reference frequency.

Abstract: A measurement device is provided. The measurement device comprises a power controller, a detector, a temperature sensor, and a processor. The power controller receives alternating-current (AC) power and transforms the AC power to direct-current (DC) power. The detector detects the DC power to generate a voltage value and a current value. The temperature sensor senses an environment temperature of the measurement device. The processor reads the voltage value, the current value, and the environment temperature and obtains an efficiency coefficient of the power controller according to the voltage value, the current value, and the environment temperature. The processor further obtains a real power consumption value corresponding to the AC power according to the efficiency coefficient.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.

Abstract: A voltage-controlled oscillator gain measurement system includes a voltage-controlled oscillator, a voltage detector, and a processor. The voltage-controlled oscillator, which is configured in a phase-locked loop circuit, generates an output signal with an output frequency according to a control signal. The control signal is generated according to the output signal divided by a scaling number. The voltage detector is configured to measure a voltage difference of the control signal. The processor adjusts the scaling number to generate an output frequency difference of the output signal, and obtains a reciprocal gain of the voltage-controlled oscillator by dividing the voltage difference by the output frequency difference.

Abstract: Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

Abstract: A measurement device is provided. The measurement device comprises a power controller, a detector, a temperature sensor, and a processor. The power controller receives alternating-current (AC) power and transforms the AC power to direct-current (DC) power. The detector detects the DC power to generate a voltage value and a current value. The temperature sensor senses an environment temperature of the measurement device. The processor reads the voltage value, the current value, and the environment temperature and obtains an efficiency coefficient of the power controller according to the voltage value, the current value, and the environment temperature. The processor further obtains a real power consumption value corresponding to the AC power according to the efficiency coefficient.

Abstract: Circuits and methods for a combined phase detector are provided. In some embodiments, circuits for a combined phase detector are provided, the circuits comprising: a tri-state phase frequency detector and charge pump that receives a reference signal and a first input signal, and that produces a first output signal; and a sub-sampling phase detector that receives the reference signal and a second input signal, and that outputs a second output signal, wherein the first output signal and the second output signal are coupled together.

Abstract: Some embodiments provide a multilayer integrated circuit, including: a semiconductor substrate including a plurality of channels extending into the substrate from a surface of the substrate; a distributed capacitor including a plurality of gates formed on the surface of the substrate over the channels, and further including an insulator between the gates and the channels, the gates being spaced apart along the surface of the substrate; an interconnect layer formed over the distributed capacitor, the interconnect layer including a plurality of conductors, at least a first conductor being connected to at least some of the gates and at least a second conductor being connected to at least some of the channels; and an inductor formed over the interconnect layer, the inductor including at least conductor arranged on a layer.

Abstract: The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.

Abstract: The provided fractional frequency divider includes a divider controlling unit for generating a divider selection signal in response to a dual-edge triggering of an input signal and a frequency dividing unit coupled to the divider controlling unit for dividing the frequency of the input signal by one of an integer and a fractional dividers in response to the dual-edge triggering and the divider selection signal to generate the output signal of the fractional frequency divider. An operation of the frequency dividing unit is not suppressed when the integer divider is employed, the operation of the frequency dividing unit is not suppressed for a period of the input signal and is suppressed for half of that period, and this cycle is kept on recurring when the fractional divider is employed. The fractional-n PLL having the fractional frequency divider is also provided.