Abstract: A polysilicon layer is formed over a substrate. The polysilicon layer is etched to form a dummy gate electrode having a top portion with a first lateral dimension and a bottom portion with a second lateral dimension. The first lateral dimension is greater than, or equal to, the second lateral dimension. The dummy gate electrode is replaced with a metal gate electrode.

Abstract: Embodiments provide a high aspect ratio via for coupling a top electrode of a vertically oriented component to the substrate, where the top electrode of the component is coupled to the via by a conductive bridge, and where the bottom electrode of the component is coupled to substrate. Some embodiments provide for mounting the component by a component wafer and separating the components while mounted to the substrate. Some embodiments provide for mounting individual components to the substrate.

Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.

Abstract: A method includes forming isolation regions extending into a semiconductor substrate, wherein semiconductor strips are located between the isolation regions, and forming a dielectric dummy strip between the isolation regions, recessing the isolation regions. Some portions of the semiconductor strips protrude higher than top surfaces of the recessed isolation regions to form protruding semiconductor fins, and a portion of the dielectric dummy strip protrudes higher than the top surfaces of the recessed isolation regions to form a dielectric dummy fin. The method further includes etching the dielectric dummy fin so that a top width of the dielectric dummy fin is smaller than a bottom width of the dielectric dummy fin. A gate stack is formed on top surfaces and sidewalls of the protruding semiconductor fins and the dielectric dummy fin.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a source/drain region formed in a semiconductor substrate, a source/drain contact structure formed over the source/drain region, and a silicide region formed between the source/drain region and the source/drain contact structure. The semiconductor device structure also includes a first insulating spacer surrounding and in direct contact with the source/drain contact structure and a second insulating spacer and a third insulating spacer respectively formed on two opposite sidewalls of the source/drain contact structure and in direct contact with an outer edge of the first insulating spacer. A first sidewall of the second insulating spacer and a second sidewall of the third insulating spacer are respectively aligned to two opposite side edges of the source/drain region.

Abstract: A method of forming a semiconductor device includes: forming a fin protruding above a substrate; forming isolation regions on opposing sides of the fin; forming a dummy gate over the fin; reducing a thickness of a lower portion of the dummy gate proximate to the isolation regions, where after reducing the thickness, a distance between opposing sidewalls of the lower portion of the dummy gate decreases as the dummy gate extends toward the isolation regions; after reducing the thickness, forming a gate fill material along at least the opposing sidewalls of the lower portion of the dummy gate; forming gate spacers along sidewalls of the dummy gate and along sidewalls of the gate fill material; and replacing the dummy gate with a metal gate.

Abstract: Several embodiments include a cooking instrument. The cooking instrument can include a heating system. The heating system can include one or more heating elements capable of emitting wireless energy into the cooking chamber. The cooking instrument can also include a control system. The control system can select a quantifiable cooking result and drive the heating system to achieve such cooking result. In at least one mode of operation, the control system can increase power density despite a power draw limit of an external power source.

Abstract: Temperature probe systems and methods include a probe body having a sharp end adapted to penetrate an edible substance, a plurality of temperature sensing elements distributed along a length of the probe body, electrical components operable to receive data signals from the plurality of temperature sensing elements, the electrical components disposed in the probe body between the sharp end and at least one of the temperature sensing elements, and an insertion aid. The electrical components may include wireless components to facilitate communications with a host cooking appliance, and the temperature sensing elements may be used to measure temperature and communicate the temperature measurements via the wireless components to the host cooking appliance. The insertion aid, the probe body, and the temperature sensing elements may include one or more heat resistant materials.

Abstract: A method includes performing an anisotropic etching on a semiconductor substrate to form a trench. The trench has vertical sidewalls and a rounded bottom connected to the vertical sidewalls. A damage removal step is performed to remove a surface layer of the semiconductor substrate, with the surface layer exposed to the trench. The rounded bottom of the trench is etched to form a slant straight bottom surface. The trench is filled to form a trench isolation region in the trench.

Abstract: A method of using a polishing pad includes applying a slurry in a first region of the polishing pad. The method further includes spreading the slurry across the first region of the polishing pad at a first rate. The method further includes spreading the slurry across a second region at a second rate different from the first rate, wherein the second region is farther from a center of the polishing pad than the first region. The method further includes spreading the slurry across a third region at a third rate different from the second rate, wherein the second region is between the third region and the first region.

Abstract: A composite ceramic substrate having multi-layer configuration includes a nitride ceramic core layer, two composite layers respectively formed on two opposite sides of the nitride ceramic core layer, and two ceramic covering layers that are respectively formed on the two composite layers. Each of the two ceramic covering layers is coated on the corresponding composite layer so as to be jointly sintered to the nitride ceramic core layer. Each of the two ceramic covering layers and the nitride ceramic core layer are of different materials, and a composite material of each of the two composite layers includes the material of the ceramic covering layer connected thereto and the material of the nitride ceramic core layer. A sum of the thicknesses of the two ceramic covering layers and the thicknesses of the two composite layers is less than or equal to a thickness of the nitride ceramic core layer.

Abstract: The disclosure is directed towards semiconductor devices and methods of manufacturing the semiconductor devices. The methods include forming fins in a device region and forming other fins in a multilayer stack of semiconductor materials in a multi-channel device region. A topmost nanostructure may be exposed in the multi-channel device region by removing a sacrificial layer from the top of the multilayer stack. Once removed, a stack of nanostructures are formed from the multilayer stack. A native oxide layer is formed to a first thickness over the topmost nanostructure and to a second thickness over the remaining nanostructures of the stack, the first thickness being greater than the second thickness. A gate dielectric is formed over the fins in the device region. A gate electrode is formed over the gate dielectric in the device region and surrounding the native oxide layer in the multi-channel device region.

Abstract: A ceramic metal composite substrate includes a metal core layer, two soldering layers, and two ceramic covering layers. The metal core layer is a metal-diamond composite layer, and the metal core layer has two metallic surfaces spaced apart from each other along a thickness direction by a predetermined thickness. The two soldering layers are respectively formed on the two metallic surfaces. The two ceramic covering layers are respectively fixed to the two metallic surfaces through the two soldering layers. Each of the two ceramic covering layers has a heat-transfer coefficient greater than or equal to 20 W/m·k, and a sum of thicknesses of the two ceramic covering layers and thicknesses of the two soldering layers is less than or equal to the predetermined thickness. Each of the two ceramic covering layers overlaps at least 80% of an area of the corresponding metallic surface along the thickness direction.

Abstract: A ceramic metal composite substrate (CMCS) includes a metal core layer, two soldering layers, and two ceramic covering layers. The metal core layer includes copper, and the metal core layer has two metallic surfaces spaced apart from each other along a thickness direction by a predetermined thickness. The two soldering layers are respectively formed on the two metallic surfaces. The two ceramic covering layers are respectively fixed to the two metallic surfaces through the two soldering layers. Each of the two ceramic covering layers has a heat-transfer coefficient greater than or equal to 20 W/m·k, and a sum of thicknesses of the two ceramic covering layers and thicknesses of the two soldering layers is less than or equal to the predetermined thickness. Each of the two ceramic covering layers overlaps at least 80% of an area of the corresponding metallic surface along the thickness direction.

Abstract: Several embodiments include a cooking appliance/instrument (e.g., oven). The cooking appliance/instrument can include a cooking chamber, a support tray adapted to hold food in the cooking chamber; and a heating system comprised of at least a heating element. The heating system is adapted to emit waves according to a particular configuration such that the emitted waves is substantially transparent or substantially opaque to the support tray and thus enabling the cooking instrument to select what to heat.

Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.

Abstract: Air curtain devices can reduce defects on semiconductor wafers when implemented on a track equipped with robotic wafer transport. The air curtain devices can be added to one or more processing devices arranged along the track to prevent defects from landing on wafer surfaces. For example, the air curtain devices can prevent volatile organic solvent mist from drifting towards processing devices on the track and preventing contamination via a wafer transport system.

Abstract: Provided is a micro-roughened electrodeposited copper foil, which comprises a micro-rough surface and multiple copper nodules. The micro-roughened electrodeposited copper foil has an Sdr of 0.01 to 0.08. With the surface characteristics, the electron path distance can be shortened, such that the micro-roughened electrodeposited copper foil can reduce the insertion loss of the copper clad laminate at high frequencies and have the desired peel strength.

Abstract: One aspect of the present disclosure pertains to a method of forming a semiconductor device. The method includes forming a gate stack over a channel region and forming a first source/drain (S/D) trench adjacent the channel region and extending into the substrate below a top surface of an isolation structure. The method includes forming a first epitaxial S/D feature in the first S/D trench and forming a first frontside metal contact over the first epitaxial S/D feature. The method further includes forming a first backside trench that exposes a bottom surface of the first epitaxial S/D feature and forming a first backside conductive feature in the first backside trench and on the exposed bottom surface of the first epitaxial S/D feature. A top surface of the first backside conductive feature is under a bottommost surface of the gate stack.

Abstract: An electronic device is disclosed. The electronic device includes a first circuit structure, a second circuit structure having a surface facing the first circuit structure, and a first electronic component disposed over the first circuit structure and supporting the second circuit structure. The electronic device also includes a second electronic component disposed adjacent to the second circuit structure and having a top surface at an elevation higher than the surface of the second circuit structure with respect to the first circuit structure.