Abstract: Embodiments of the present disclosure provide semiconductor device structures and methods of forming the same. The structure includes a source/drain region disposed over a substrate, a gate electrode layer disposed over the substrate, a first gate spacer disposed between the gate electrode layer and the source/drain region, and a dielectric spacer disposed between the gate electrode layer and the source/drain region. A first portion of the dielectric spacer is in contact with a first portion of the first gate spacer. The structure further includes a sacrificial layer disposed between a second portion of the first gate spacer and a second portion of the dielectric spacer.

Abstract: A photonic device, structure, and fabrication method that includes a substrate having a topside oxide layer formed thereon. The structure also includes a silicon layer that is formed on the topside oxide layer, and one or more waveguide components that are formed in the silicon layer. In addition, the structure includes a reflection device trench structure that is formed in the silicon layer, and which includes a first oblique plane, a bottom plane, and a second oblique plane. The photonic structure also includes a reflection device that is formed adjacent to the first oblique plane, and which has a reflection device angle relative to the bottom plane and configured to direct light into a waveguide component.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a first top oxide layer and a silicon layer that is formed on the first top oxide layer. The structure further includes a plurality of rib waveguide components that are formed in the silicon layer. A first rib waveguide component of the plurality includes first contact holes having a first contact hole depth, and a second rib waveguide component of the plurality includes second contact holes having a second contact hole depth, such that the depths of the first contact hole and the second contact hole are different.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: A photonic device structure and method of fabricating the same. The structure includes a substrate that has a topside oxide layer and a silicon layer that is formed on the topside oxide layer. The structure further includes a rib waveguide component formed in the silicon layer and that includes contact holes. The contact holes include a contact hole depth, and a contact hole trench that is formed in the silicon layer and which has a first sidewall, a second sidewall, and a bottom surface. The contact hole further includes a contact etch stop layer formed in the contact hole trench.

Abstract: An interconnect fabrication method is disclosed herein that utilizes a disposable etch stop hard mask over a gate structure during source/drain contact formation and replaces the disposable etch stop hard mask with a dielectric feature (in some embodiments, dielectric layers having a lower dielectric constant than a dielectric constant of dielectric layers of the disposable etch stop hard mask) before gate contact formation. An exemplary device includes a contact etch stop layer (CESL) having a first sidewall CESL portion and a second sidewall CESL portion separated by a spacing and a dielectric feature disposed over a gate structure, where the dielectric feature and the gate structure fill the spacing between the first sidewall CESL portion and the second sidewall CESL portion. The dielectric feature includes a bulk dielectric over a dielectric liner. The dielectric liner separates the bulk dielectric from the gate structure and the CESL.

Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes a first conductive pattern disposed within a first region from a top view perspective and extending along a first direction, a first phase shift circuit disposed within the first region, a first transmission circuit disposed within a second region from the top view perspective, and a first gate conductor extending from the first region to the second region along a second direction perpendicular to the first direction. The first phase shift circuit and the first transmission circuit are electrically connected with the first conductive pattern through the first gate conductor.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming semiconductor fins on a substrate. A first dummy gate is formed over the semiconductor fins. A recess is formed in the first dummy gate, and the recess is disposed between the semiconductor fins. A dummy fin material is formed in the recess. A portion of the dummy fin material is removed to expose an upper surface of the first dummy gate and to form a dummy fin. A second dummy gate is formed on the exposed upper surface of the first dummy gate.

Abstract: Contact structures and methods of forming the same are provided. A method according to the present disclosure includes receiving a workpiece including a conductive feature embedded in a first dielectric layer, treating the workpiece with a nitrogen-containing plasma, after the treating, depositing a first etch stop layer (ESL) over the workpiece, depositing a second ESL over the first ESL, depositing a second dielectric layer over the second ESL, forming an opening through the second dielectric layer, the second ESL and the first ESL to expose the conductive feature, and forming a contact via in the opening. The first ESL includes aluminum nitride or silicon carbonitride and the second ESL includes aluminum oxide or silicon oxycarbide.

Abstract: A light emitting diode package structure and a method for manufacturing the same are provided. The LED package structure includes a substrate having a first and a second surface opposite to each other, a conductive structure including a first and a second conductive structure electrically connected with each other, a first gold layer disposed on the first conductive structure, a second gold layer disposed on the second conductive structure, an LED chip disposed on the first gold layer, and a package layer disposed on the first surface and encapsulating the first conductive structure, the first gold layer, and the LED chip. The first conductive structure is disposed on the first surface. The second conductive structure is disposed on the second surface. A thickness of the first gold layer is greater than 1 ?m. The second conductive structure is completely covered by the second gold layer.

Abstract: A memory device includes a stack structure, a first stop layer, a dielectric layer, at least one separation wall and a conductive plug. The stacked structure is located over a substrate. The stacked structure has an opening exposing a stepped structure of the stacked structure. The first stop layer covers the stepped structure and at least at least one portion of sidewalls of the opening. The dielectric layer fills the opening and covers the first stop layer. The separation wall extends through the dielectric layer and the first stop layer in the opening. The conductive plug extends through the dielectric layer and the first stop layer, and is electrically connected to the stepped structure. The memory device may be a 3D NAND flash memory with high capacity and high performance.

Abstract: A deep trench resistor structure and methods of forming the same are described. The structure includes a first trench located in a first dielectric material, a first layer disposed over the first dielectric material, a second layer disposed on the first layer, a second dielectric material disposed over the second layer, and a tunable device in contact with the first layer. The tunable device includes a semiconductor-containing layer in contact with the first layer, a dielectric layer disposed on the semiconductor-containing layer, and a metal-containing layer disposed on the dielectric layer.

Abstract: In some embodiments, an integrated circuit device includes a substrate having a frontside and a backside; one or more active semiconductor devices formed on the frontside of the substrate; conductive paths formed on the frontside of the substrate; and conductive paths formed on the backside of the substrate. At least some of the conductive paths formed on the backside of the substrate, and as least some of the conductive paths formed on the front side of the substrate, are signal paths among the active semiconductor devices. In in some embodiments, other conductive paths formed on the backside of the substrate are power grid lines for powering at least some of the active semiconductor devices.

Abstract: The present disclosure provides an optical packaging structure and a backlight module with the optical packaging structure. The optical packaging structure includes a light-emitting chip, a packaging layer, a fluorescent layer, a lens structure, and a reflecting layer. The light-emitting chip includes a light-emitting surface, a connecting surface, and a side surface. The packaging layer covers the light-emitting surface and the first side surface. The connecting surface is exposed from the packaging layer. The fluorescent layer is disposed on the packaging layer, and covers on the light-emitting surface and the first side surface. The lens structure is disposed on a top surface of the fluorescent layer. A surface of the lens structure is recessed towards the light-emitting chip to form a curved surface. The reflecting layer is disposed on the curved surface.

Abstract: A method includes simultaneously forming a first dummy gate stack and a second dummy gate stack on a first portion and a second portion of a protruding fin, simultaneously removing a first gate electrode of the first dummy gate stack and a second gate electrode of the second dummy gate stack to form a first trench and a second trench, respectively, forming an etching mask, wherein the etching mask fills the first trench and the second trench, patterning the etching mask to remove the etching mask from the first trench, removing a first dummy gate dielectric of the first dummy gate stack, with the etching mask protecting a second dummy gate dielectric of the second dummy gate stack from being removed, and forming a first replacement gate stack and a second replacement gate stack in the first trench and the second trench, respectively.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A method includes forming a photoresist layer over a wafer; aligning a first photomask with a first area of the wafer; performing a first exposure process to a first portion of the photoresist layer within the first area of the wafer; aligning a second photomask with a second area of the wafer, wherein aligning the first photomask and aligning the second photomask are performed using an alignment mark within a stitching zone of the wafer, the stitching zone being an overlapping region of the first area and the second area; performing a second exposure process to a second portion of the photoresist layer within the second area of the wafer; and performing a development process to remove the first and second portions of the photoresist layer.

Abstract: The present disclosure describes a resistor structure with a dielectric layer, trenches, a metal layer, a semiconductor layer, and an insulating layer. The dielectric layer is disposed above electrical components formed on a substrate. The trenches are disposed in the dielectric layer and separated from each other by a dielectric region of the dielectric layer. The metal layer is disposed on a bottom surface and side surfaces of each of the trenches and on a top surface of the dielectric region. The semiconductor layer is disposed on a bottom surface, side surfaces, and a top surface of the metal layer. The insulating layer is disposed in the trenches and in contact with side surfaces of the semiconductor layer and on a top surface of the semiconductor layer.

Abstract: The present disclosure relates to adaptively overlapping redo writes. A log writer, while operating in a thin mode, may assign a first log writer group of a plurality of log writer groups to write one or more first redo log records to an online redo log in response to determining that a pipelining parameter is satisfied. The thin mode may be associated with one or more target sizes that are less than one or more target sizes associated with a thick mode. The log writer may determine to operate the thick mode based at least in part on at least a portion of the plurality of log writer groups being unavailable to write one or more second redo log records to the online redo log.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.