Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.

Abstract: An authorized access list generation method including: at least one network service providing device registering for an authorized access list notification service with a server, the authorized access list including at least one authorization related record of at least one legitimate user device; the legitimate user device outputting a user ID to the server to log into the server, and directly sending an access request to a target network service provider after logging into the server, and continuing to provide an IP address being used and a device ID to the server to update a corresponding authorization related record; and the target network service providing device comparing the IP address, stored in each authorization related record of the authorized access list, with the IP address of a user device issuing an access request, and rejecting the access request if no matched result is found.

Abstract: A detection method for a touch device includes transmitting a first uplink signal conforming to a first protocol of a first active stylus and transmitting a second uplink signal conforming to a second protocol of a second active stylus. A chronological sequence of the first uplink signal and the second uplink signal is based at least in part on whether the first active stylus or the second active stylus has just left a detection range of the touch device.

Abstract: A network malicious behavior detection method, including: checking each piece of network packet to determine whether a protocol payload contained therein matches an element in a predetermined protocol payload set, marking each piece of the network packet as a suspicious network packet if the check result is true, and transferring each piece of the network packet to a target device if the check result is false; and performing a malicious behavior checking process on at least one piece of the suspicious network packet, blocking the transfer of at least one piece of the suspicious network packet to the target device if the check result is true, and enabling the transfer of at least one piece of the suspicious network packet to the target device if the check result is false.

Abstract: A detection method for a touch device includes transmitting a first uplink signal conforming to a first protocol of a first active stylus and transmitting a second uplink signal conforming to a second protocol of a second active stylus. A chronological sequence of the first uplink signal and the second uplink signal is based at least in part on whether the first active stylus or the second active stylus has just left a detection range of the touch device.

Abstract: In an internal network monitoring method for monitoring an internal network, a specified network packet, which is scheduled to be transmitted via a specified path, is inspected. A packet characteristic is extracted from a data link layer of the specified network packet. The specified network packet is directly transmitted via the specified path if the packet characteristic does not comply with a preset condition. The specified network packet is redirected to be transmitted via another path different from the specified path or mirroring the specified network packet to create a mirror packet if the packet characteristic complies with the preset condition.

Abstract: An authorized access list generation method including: at least one network service providing device registering for an authorized access list notification service with a server, the authorized access list including at least one authorization related record of at least one legitimate user device; the legitimate user device outputting a user ID to the server to log into the server, and directly sending an access request to a target network service provider after logging into the server, and continuing to provide an IP address being used and a device ID to the server to update a corresponding authorization related record; and the target network service providing device comparing the IP address, stored in each authorization related record of the authorized access list, with the IP address of a user device issuing an access request, and rejecting the access request if no matched result is found.

Abstract: A network malicious behavior detection method, including: checking each piece of network packet to determine whether a protocol payload contained therein matches an element in a predetermined protocol payload set, marking each piece of the network packet as a suspicious network packet if the check result is true, and transferring each piece of the network packet to a target device if the check result is false; and performing a malicious behavior checking process on at least one piece of the suspicious network packet, blocking the transfer of at least one piece of the suspicious network packet to the target device if the check result is true, and enabling the transfer of at least one piece of the suspicious network packet to the target device if the check result is false.

Abstract: In an internal network monitoring method for monitoring an internal network, a specified network packet, which is scheduled to be transmitted via a specified path, is inspected. A packet characteristic is extracted from a data link layer of the specified network packet. The specified network packet is directly transmitted via the specified path if the packet characteristic does not comply with a preset condition. The specified network packet is redirected to be transmitted via another path different from the specified path or mirroring the specified network packet to create a mirror packet if the packet characteristic complies with the preset condition.

Abstract: A touch system includes a touch panel; an active pen configured to generate a signal; and a touch controller electrically connected to the touch panel and configured to detect the signal. When the touch controller supports at least two protocols, a protocol of the touch controller is automatically switched to one of the at least two protocols. The active pen automatically detects the one of the at least two protocols, and a protocol of the active pen is switched to the one of the at least two protocols.

Abstract: A touch system includes a touch panel; an active pen configured to generate a signal; and a touch controller electrically connected to the touch panel and configured to detect the signal. When the touch controller supports at least two protocols, a protocol of the touch controller is automatically switched to one of the at least two protocols. The active pen automatically detects the one of the at least two protocols, and a protocol of the active pen is switched to the one of the at least two protocols.

Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Abstract: A random code generator includes a differential cell array, a power circuit, a voltage detector, a control circuit and a read/write circuit. The power circuit provides a supply voltage to a node. The differential cell array includes plural differential cells. Each differential cell includes two sub-cells. The two sub-cells have process variations. During the enrollment, one sub-cell is programmed, and the other sub-cell is subjected to a program inhibition. In addition, a random code is generated according to the storage state of the differential cell.

Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Abstract: A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data “1” or digital data “0”. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line. The second P+ source doping region and the second P+ drain doping region define a floating gate channel region under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed.

Abstract: A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data “1” or digital data “0”. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line. The second P+ source doping region and the second P+ drain doping region define a floating gate channel region under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed.