Patents by Inventor Shih Chan WEI

Shih Chan WEI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12315791
    Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: May 27, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Han Yang, Lung-Hui Chen, Shih Chan Wei, Kuan-Yu Chen
  • Publication number: 20250038102
    Abstract: A metallization structure of an integrated circuit (IC) includes: an intermetal dielectric (IMD) layer; a patterned metal layer embedded in the IMD layer; a patterned top metal layer disposed on the IMD layer; electrical vias comprising via material passing through the IMD layer and connecting the patterned top metal layer and the patterned metal layer embedded in the IMD layer; and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes: a first capacitor metal layer comprising the via material contacting an MIM capacitor landing area of the patterned metal layer embedded in the IMD layer; a second capacitor metal layer comprising the via material contacting a first MIM capacitor terminal area of the patterned top metal layer; and an insulator layer disposed between the first capacitor metal layer and the second capacitor metal layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Inventors: Chi-Han Yang, Lung Huei Chen, Shih Chan Wei, Kuan-Yu Chen
  • Publication number: 20240105815
    Abstract: A semiconductor structure and method of manufacture is provided. In some embodiments, a semiconductor structure includes a semiconductor layer, a first isolation structure in the semiconductor layer, a first gate structure adjacent a first side of the first isolation structure, a first source/drain region adjacent a second side of the first isolation structure, a second source/drain region adjacent the first gate structure, and a first conductive field plate at least partially embedded in the first isolation structure.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 28, 2024
    Inventors: Chin-Yi HUANG, Shih Chan WEI, Wei Kai SHIH