Patents by Inventor Shih-Che Chen

Shih-Che Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10892235
    Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10795270
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
  • Patent number: 10685868
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: June 16, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • Patent number: 10666438
    Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Che Tsai, Cheng Hung Lee, Shih-Lien Linus Lu, Yi-Ju Chen
  • Publication number: 20200161764
    Abstract: A dual-band antenna is provided. The dual-band antenna includes a first antenna, a second antenna, and a grounding component. The first antenna has a first feed point for transceiving a first signal. The second antenna has a second feed point. The grounding component is electrically coupled to the first feed point and the second feed point, wherein the grounding component forms a first path and a second path between the first feed point and the second feed point, wherein a first path length of the first path and a second path length of the second path are integer multiples of a first wavelength of the first signal.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 21, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wen-Jiao Liao, Jhin-Ciang Chen, Shih-Chia Liu, Liang-Che Chou, Yen-Hao Yu, Li-Chun Lee
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200144207
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Application
    Filed: December 20, 2019
    Publication date: May 7, 2020
    Inventors: Sheng-Chau CHEN, Shih-Pei CHOU, Ming-Che LEE, Kuo-Ming WU, Cheng-Hsien CHOU, Cheng-Yuan TSAI, Yeur-Luen TU
  • Publication number: 20200129838
    Abstract: A training method, training system and non-transitory computer-readable medium are provided in this disclosure. The training method includes the following operations: receiving a training script; wherein the training script includes at least one training stage corresponding to a timeline, and a training time and a training goal corresponding to the least one training stage; generating a voice information according to the training script, and outputting the voice information by an audio outputting unit; receiving a physiological signal sensed by a physiological signal sensor in the at least one training stage, and analyzing the physiological signal utilized an analyzing module to obtain an analysis result; and determining whether the analysis result meets the training goal corresponding to the at least one training stage; if not, outputting a voice reminding by the audio outputting unit.
    Type: Application
    Filed: November 28, 2018
    Publication date: April 30, 2020
    Inventors: Yong-Ruei CHEN, Ping-Che YANG, Shih-Chun CHOU
  • Patent number: 10586902
    Abstract: A light-emitting device includes a light-emitting structure with a side surface, and a reflective layer covering the side surface. The light-emitting structure has a first light-emitting angle and a second light-emitting angle. The difference between the first light-emitting angle and the second light-emitting angle is larger than 15°.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 10, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Liang Liu, Ming-Chi Hsu, Shih-An Liao, Chun-Hung Liu, Zhi-Ting Ye, Cheng-Teng Ye, Po-Chang Chen, Sheng-Che Chiou
  • Publication number: 20200075294
    Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.
    Type: Application
    Filed: May 24, 2019
    Publication date: March 5, 2020
    Inventors: Jr-Sheng CHEN, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chen-Chun Yan
  • Publication number: 20200066657
    Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.
    Type: Application
    Filed: September 19, 2018
    Publication date: February 27, 2020
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Publication number: 20200043705
    Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 6, 2020
    Inventors: Jr-Sheng CHEN, An-Chi Li, Shih-Che Huang, Chih-Hsien Hsu, Zhi-Hao Huang, Alex Wang, Yu-Pei Chiang, Chen-Chun Yan
  • Publication number: 20200020364
    Abstract: A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates.
    Type: Application
    Filed: October 15, 2018
    Publication date: January 16, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Che TSAI, Cheng Hung LEE, Shih-Lien Linus LU, Yi-Ju CHEN
  • Patent number: 10535653
    Abstract: A semiconductor structure includes a pair of gate structures and an isolation structure. Each of the gate structures includes a work function metal, a gate, and a barrier layer between the work function metal and the gate. The isolation structure is disposed between the gate structures. The barrier layer covers a sidewall of the isolation structure.
    Type: Grant
    Filed: December 17, 2017
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yi-Jen Chen, Chun-Sheng Liang, Shu-Hui Wang, Shih-Hsun Chang, Hsin-Che Chiang
  • Patent number: 10529629
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10522487
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a semiconductive substrate and an interconnect structure over the semiconductive substrate. The semiconductor structure also comprises a bond pad in the semiconductive substrate and coupled to the metal layer. The bond pad comprises two conductive layers.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chau Chen, Shih-Pei Chou, Ming-Che Lee, Kuo-Ming Wu, Cheng-Hsien Chou, Cheng-Yuan Tsai, Yeur-Luen Tu
  • Publication number: 20190393080
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Application
    Filed: August 28, 2019
    Publication date: December 26, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • Publication number: 20190333826
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: April 30, 2018
    Publication date: October 31, 2019
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Patent number: 10438842
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: October 8, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Ingtegrated Circuit Co., Ltd.
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen
  • Publication number: 20190206724
    Abstract: A method of fabricating a contact hole includes the steps of providing a conductive line, a mask layer covering and contacting the conductive line, a high-k dielectric layer covering and contacting the mask layer, and a first silicon oxide layer covering and contacting the high-k dielectric layer, wherein the high-k dielectric layer includes a first metal oxide layer, a second metal oxide layer and a third metal oxide layer stacked from bottom to top. A dry etching process is performed to etch the first silicon oxide layer, the high-k dielectric layer, and the mask layer to expose the conductive line and form a contact hole. Finally, a wet etching process is performed to etch the first silicon oxide layer, the third metal oxide layer and the second metal oxide layer to widen the contact hole, and the first metal oxide layer remains after the wet etching process.
    Type: Application
    Filed: June 8, 2018
    Publication date: July 4, 2019
    Inventors: Feng-Yi Chang, Shih-Fang Tzou, Fu-Che Lee, Hsin-Yu Chiang, Yu-Ching Chen