Patents by Inventor Shih-Che Huang

Shih-Che Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210109307
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Application
    Filed: October 9, 2020
    Publication date: April 15, 2021
    Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
  • Patent number: 10978391
    Abstract: A connection structure of a semiconductor device is provided in the present invention. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: April 13, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chen-Yi Weng, Shih-Che Huang, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10972292
    Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Che Tsai, Shih-Lien Linus Lu, Cheng Hung Lee, Chia-En Huang
  • Publication number: 20210098376
    Abstract: Vias, along with methods for fabricating vias, are disclosed that exhibit reduced capacitance and resistance. An exemplary interconnect structure includes a first source/drain contact and a second source/drain contact disposed in a dielectric layer. The first source/drain contact physically contacts a first source/drain feature and the second source/drain contact physically contacts a second source/drain feature. A first via having a first via layer configuration, a second via having a second via layer configuration, and a third via having a third via layer configuration are disposed in the dielectric layer. The first via and the second via extend into and physically contact the first source/drain contact and the second source/drain contact, respectively. A first thickness of the first via and a second thickness of the second via are the same. The third via physically contacts a gate structure, which is disposed between the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: August 4, 2020
    Publication date: April 1, 2021
    Inventors: Shih-Che Lin, Po-Yu Huang, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Wei-Jung Lin, Chen-Yuan Kao
  • Publication number: 20210091190
    Abstract: A source/drain is disposed over a substrate. A source/drain contact is disposed over the source/drain. A first via is disposed over the source/drain contact. The first via has a laterally-protruding bottom portion and a top portion that is disposed over the laterally-protruding bottom portion.
    Type: Application
    Filed: June 11, 2020
    Publication date: March 25, 2021
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang
  • Publication number: 20210082839
    Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.
    Type: Application
    Filed: November 24, 2020
    Publication date: March 18, 2021
    Applicant: United Microelectronics Corp.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10939976
    Abstract: Disclosed is a minimally invasive instrument with instant force feedback function, including a minimally invasive device, a sensing device, a computing device, and a warning device. The minimally invasive device may have an invasive portion, which may enter the human body to perform surgical operations. The sensing device is provided on the invasive portion of the minimally invasive device and may include a flexible conductive film, a plurality of bionic films and a plurality of liquid beads. The plurality of bionic films may be provided on a flexible conductive film. Each of the plurality of liquid beads may be covered by each of the plurality of bionic films. The computing device may be electrically connected to the flexible conductive film. The warning device may receive a warning signal and generate a warning message.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 9, 2021
    Assignee: Show-Chwan Memorial Hospital
    Inventors: Shih-Chi Chan, Kai-Che Liu, Shih-Wei Huang, Hsien-Yeh Chen, Tien-Li Chang
  • Publication number: 20210018848
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Application
    Filed: October 5, 2020
    Publication date: January 21, 2021
    Inventors: Ta-Ching YU, Shih-Che WANG, Shu-Hao CHANG, Yi-Hao CHEN, Chen-Yen KAO, Te-Chih HUANG, Yuan-Fu HSU
  • Patent number: 10892235
    Abstract: A die seal ring and a manufacturing method thereof are provided. The die seal ring includes a substrate, a dielectric layer, and conductive layers. The dielectric layer is disposed on the substrate. The conductive layers are stacked on the substrate and located in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is disposed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is disposed between a sidewall of the second conductive portion and the dielectric layer. The die seal ring and the manufacturing method thereof can effectively prevent cracks generated during the die sawing process from damaging the circuit structure.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 12, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Che Huang, Shih-Hsien Chen, Ching-Li Yang, Chih-Sheng Chang
  • Patent number: 10795270
    Abstract: Embodiments of the present disclosure relate to methods for defect inspection. After pattern features are formed in a structure layer, a dummy filling material having dissimilar optical properties from the structure layer is filled in the pattern features. The dissimilar optical properties between materials in the pattern features and the structure layer increase contrast in images captured by an inspection tool, thus increasing the defect capture rate.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ta-Ching Yu, Shih-Che Wang, Shu-Hao Chang, Yi-Hao Chen, Chen-Yen Kao, Te-Chih Huang, Yuan-Fu Hsu
  • Publication number: 20200226386
    Abstract: A highlight processing method includes: obtaining a frame sequence that includes frames each having image contents associated with at least one object, wherein object pose estimation is performed upon each frame of the frame sequence to generate an object pose estimation result of each frame, and further includes determining at least one of a start point and an end point of a highlight interval, wherein comparison of object pose estimation results of different frames is involved in determination of at least one of the start point and the end point of the highlight interval.
    Type: Application
    Filed: August 19, 2019
    Publication date: July 16, 2020
    Inventors: Shih-Jung Chuang, Yan-Che Chuang, Chun-Nan Li, Yu-Hsuan Huang, Chih-Chung Chiang
  • Publication number: 20200212048
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Application
    Filed: January 27, 2019
    Publication date: July 2, 2020
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Patent number: 10700071
    Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
    Type: Grant
    Filed: January 27, 2019
    Date of Patent: June 30, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Gang-Yi Lin, Shih-Fang Tzou, Fu-Che Lee, Feng-Yi Chang, Ying-Chih Lin, Kai-Lou Huang, Yi-Ching Chang
  • Publication number: 20200176574
    Abstract: Vertical interconnect structures and methods of forming are provided. The vertical interconnect structures may be formed by partially filling a first opening through one or more dielectric layers with layers of conductive materials. A second opening is formed in a dielectric layer such that a depth of the first opening after partially filling with the layers of conductive materials is close to a depth of the second opening. The remaining portion of the first opening and the second opening may then be simultaneously filled.
    Type: Application
    Filed: May 10, 2019
    Publication date: June 4, 2020
    Inventors: Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang, Rueijer Lin, Chen-Yuan Kao
  • Publication number: 20200160088
    Abstract: An image adaptive feature extraction method includes dividing an image into a plurality of blocks, performing a feature extraction processing on the plurality of blocks, and obtaining a block feature from each of the plurality of blocks after the feature extraction processing; calculating each block feature by means of a support vector machine (SVM) classifier, wherein each block feature is calculated to obtain a hyperplane normal vector; setting a threshold value, determining the block feature according to the hyperplane normal vector, recording the block as an adaptive feature block when a value of the hyperplane normal vector is higher than the threshold value, and integrating each adaptive feature block to form an adaptive feature image. Because an image adaptive feature extraction process is performed before a pedestrian image detection is calculated, and effective feature data is then selected, computational efficiency is boosted and detection pedestrian error probability is reduced.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 21, 2020
    Inventors: Shih-Shinh Huang, Shih-Che Chien, Feng-Chia Chang, Yu-Sung Hsiao, Chien-Hao Hsiao
  • Publication number: 20200152521
    Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 14, 2020
    Inventors: Ju-Li Huang, Hsin-Che Chiang, Ju-Yuan Tzeng, Wei-Ze Xu, Yueh-Yi Chen, Shu-Hui Wang, Shih-Hsun Chang
  • Publication number: 20200136839
    Abstract: Disclosed is an input/output circuit for a physical unclonable function generator circuit. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, and at least one input/output (I/O) circuit each coupled to at least two neighboring columns of the PUF cell array, wherein the at least one I/O circuit each comprises a sense amplifier (SA) with no cross-coupled pair of transistors, wherein the SA comprises two cross-coupled inverters with no access transistor and a SA enable transistor, and wherein the at least one I/O circuit each is configured to access and determine logical states of at least two bit cells in the at least two neighboring columns; and based on the determined logical states of the plurality of bit cells, to generate a PUF signature.
    Type: Application
    Filed: April 12, 2019
    Publication date: April 30, 2020
    Inventors: Jui-Che TSAI, Shih-Lien Linus LU, Cheng Hung LEE, Chia-En HUANG
  • Publication number: 20200135641
    Abstract: Methods to form vertically conducting and laterally conducting low-cost resistor structures utilizing dual-resistivity conductive materials are provided. The dual-resistivity conductive materials are deposited in openings in a dielectric layer using a single deposition process step. A high-resistivity ?-phase of tungsten is stabilized by pre-treating portions of the dielectric material with impurities. The portions of the dielectric material in which impurities are incorporated encompass regions laterally adjacent to where high-resistivity ?-W is desired. During a subsequent tungsten deposition step the impurities may out-diffuse and get incorporated in the tungsten, thereby stabilizing the metal in the high-resistivity ?-W phase. The ?-W converts to a low-resistivity ?-phase of tungsten in the regions not pre-treated with impurities.
    Type: Application
    Filed: August 5, 2019
    Publication date: April 30, 2020
    Inventors: Jia-En Lee, Po-Yu Huang, Shih-Che Lin, Chao-Hsun Wang, Kuo-Yi Chao, Mei-Yun Wang, Feng-Yu Chang
  • Publication number: 20200124967
    Abstract: A method of supplying a chemical solution to a photolithography system. The chemical solution is pumped from a variable-volume buffer tank. The pumped chemical solution is dispensed in a spin-coater. The variable-volume buffer tank is refilled by emptying a storage container filled with the chemical solution into the variable-volume buffer tank.
    Type: Application
    Filed: December 17, 2019
    Publication date: April 23, 2020
    Inventors: Wen-Zhan Zhou, Heng-Jen Lee, Hsu-Yuan Liu, Yu-Chen Huang, Cheng-Han Wu, Shih-Che Wang, Ho-Yung David Hwang
  • Patent number: 10621466
    Abstract: A method for extracting features of a thermal image is provided. The method includes: reading a thermal image, and dividing the thermal image into a plurality of block images; and extracting a histogram of oriented gradient (HOG) feature histogram from each of the plurality of block images, and transforming the HOG feature histogram of each of the plurality of block images into a symmetric weighting HOG (SW-HOG) feature histogram. The SW-HOG feature histogram is obtained by multiplying a histogram of gradient intensity distribution by a block weighting. The method increases weightings of blocks which cover human contours and reduces weightings of blocks of an internal region of a human appearance through analyzing thermal lightness difference of regions within blocks, to reduce the influence of clothes in the internal region and the influence of the background region.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: April 14, 2020
    Assignee: National Chung-Shan Institute of Science and Technology
    Inventors: Shih-Shinh Huang, Shih-Che Chien, Feng-Chia Chang, Chien-Hao Hsiao, Yu-Sung Hsiao